Attached files
Exhibit 10.1
Certain confidential information contained in this document, marked by brackets, has been omitted and filed separately with the Securities and Exchange Commission pursuant to Rule 24b-2 of the Securities Exchange Act of 1934, as amended.
MIPS CORE TECHNOLOGY SCHEDULE
for the
Licensed Technology
Cavium Networks, Inc. (“Licensee”) desires to license from MIPS and MIPS is willing to license to Licensee the intellectual property associated with the Licensed Technology described below subject to the terms and conditions of the Master Technology License Agreement for MIPS Architecture and MIPS Cores between MIPS and Licensee effective as of December 30, 2003 (the “Agreement” or “Master Agreement”) and this MIPS Core Technology Schedule (the “Technology Schedule”) to be effective as of September 29, 2010 (the “Schedule Effective Date”). All of the terms and conditions of the Master Agreement are incorporated herein and shall apply to this Technology Schedule. Unless otherwise indicated, all capitalized terms shall have the meanings assigned in the Master Agreement. This Technology Schedule shall supersede and replace the Technology Schedule for MIPS64 Architecture effective as of December 30, 2003 between MIPS and Licensee, as previously amended (the “2003 Technology Schedule”).
1. Licensed Technology:
| (1) | MIPS64® Architecture |
| (2) | MIPS32® M14Kc™ Synthesizable Processor Core |
| (3) | MIPS32® M14K™ Synthesizable Processor Core |
| (4) | MIPS32® 24KEc™ Synthesizable Processor Core |
| (5) | MIPS32® 24KEf™ Synthesizable Processor Core |
| (6) | MIPS32® 34Kc™ Synthesizable Processor Core (the “34Kc Core”) |
| (7) | MIPS32® 34Kf™ Synthesizable Processor Core (the “34Kf Core”) |
| (8) | MIPS32® 1004Kc™ Coherent Processing System (CPS) Synthesizable Core |
| (9) | MIPS32® 1004Kf™ Coherent Processing System (CPS) Synthesizable Core |
| (10) | MIPS32® 74Kc™ Synthesizable Processor Core |
| (11) | MIPS32® 74Kf™ Synthesizable Processor Core |
| (12) | MIPS® SOC-it® L2 Cache Controller |
2. MIPS Deliverables: The MIPS Deliverables (including the confidentiality level and delivery schedule for each MIPS Deliverable) for each Licensed Technology are as set forth on Exhibit B.
3. Third Party IP: Not applicable
4. Authorized Foundry: The following foundries are each an Authorized Foundry in the location(s) described below:
[*]
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MIPS Confidential
Certain confidential information contained in this document, marked by brackets, has been omitted and filed separately with the Securities and Exchange Commission pursuant to Rule 24b-2 of the Securities Exchange Act of 1934, as amended.
Upon written approval from MIPS (Exhibit C to the Master Agreement may be used for this purpose), additional foundries may be added as an “Authorized Foundry” from time to time during the term of this Technology Schedule.
5. Licensee Application: Licensee Chips may be designed for the following applications: all applications. The reference to “the applicable Licensee Application” in Section 1.4 of the Master Agreement is not intended as, and shall not be interpreted to be, any limitation on the applications for which any Licensee Chips may be designed under this Technology Schedule.
6. Distribution Rights: Notwithstanding anything in Section 1.4 of the Master Agreement to the contrary, Licensee may distribute Licensee Chips as [*] or packaged integrated circuits which packaged integrated circuits may be distributed as packaged parts or as part of a board or subsystem. Notwithstanding anything in Section 1.4 of the Master Agreement to the contrary, portions of a “Licensee Chip” that do not consist of Licensed MIPS Core(s), Licensed MIPS Architecture Compatible Core(s) or Licensed Hard Core Implementation(s) may be designed, in whole or part, for Licensee by third parties, without restrictions of any kind, and no involvement of third parties in the design of such portions of a chip will disqualify such chip from being a “Licensee Chip,” provided, however, that the third parties do not receive any MIPS Confidential Information, unless otherwise approved by MIPS in writing.
7. License Fees:
7.1 The Unlimited Use Fee: In accordance with the provisions of Section 7.1 of this Technology Schedule, Licensee shall pay MIPS a nonrefundable Unlimited Use license fee of US$[*] in consideration for acquiring the license rights set forth in Section 2 of the Master Agreement for the Licensee Chips developed under this Technology Schedule, which fee is due [*] and shall be paid by Licensee as follows: [*]. Licensee shall provide MIPS with the requisite purchase order in the amount of said license fee as soon as practicable after execution of this Technology Schedule. “Unlimited Use” shall mean an unlimited number of uses with an unlimited number of instantiations of Licensed Hard Core Implementations in Licensee Chips [*] prior to the termination or expiration of this Technology Schedule and subject to the terms set forth below.
For the avoidance of doubt, and notwithstanding anything in Section 2.1 of the Master Agreement to the contrary (including, without limitation, the use of the singular form of the terms “Licensed Hard Core Implementation” and “Authorized Foundry”), the Unlimited Use license fee covers, and the licenses granted by MIPS to Licensee in Section 2.1 of the Master Agreement shall include, the right to develop multiple Synthesizable Licensed MIPS Cores that are Licensed MIPS Architecture Compatible Cores and to develop and have developed as permitted in Section 2.1 multiple Licensed Hard Core Implementations from the same, and to design these into multiple Licensee Chips which may be targeted at multiple applications during the term of this Technology Schedule, and to target Licensed Hard Core Implementations for manufacture at multiple Authorized Foundries, and to have Licensed Hard Core Implementations as incorporated into Licensee Chips manufactured at multiple Authorized Foundries. Further, notwithstanding anything in Section 2.1 of the Master Agreement to the contrary, the rights and licenses granted by MIPS under MIPS Intellectual Property Rights in the MIPS Deliverables for the Licensed Technology under this Technology Schedule shall include [*] which relate to Licensee’s
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MIPS Confidential
Certain confidential information contained in this document, marked by brackets, has been omitted and filed separately with the Securities and Exchange Commission pursuant to Rule 24b-2 of the Securities Exchange Act of 1934, as amended.
permitted development of Synthesizable Licensed MIPS Cores but only to the extent such Synthesizable Licensed MIPS Cores implement the Licensed MIPS Architecture, permitted development of Licensed Hard Core Implementations from such Synthesizable Licensed MIPS Cores but only to the extent such Licensed Hard Core Implementations implement the Licensed MIPS Architecture, permitted design of such Licensed Hard Core Implementations into Licensee Chips, permitted manufacture of such Licensed Hard Core Implementations as incorporated in such Licensee Chips made at Authorized Foundries or permitted use, importation, offering for sale, sale or other distribution of such Licensed Hard Core Implementations as incorporated in such Licensee Chips.
7.2 Additional Per Use Fees: None.
8. Royalties:
8.1 Licensee shall pay MIPS a nonrefundable royalty for each unit of a Licensee Chip made commercially available and shipped after the Effective Date of this Technology Schedule (the “2010 Licensee Chip(s)”) for which royalty has accrued in accordance with the Master Agreement and pursuant to this Technology Schedule equal to [*] percent ([*]%) of Net Revenue, [*]. If a 2010 Licensee Chip is shipped as a part of a board or sub-system or multi-chip module the royalty for such 2010 Licensee Chip shall be calculated [*]. Notwithstanding the foregoing, in the event that a Licensee Chip [*], the royalty for each unit of a Licensee Chip shall be [*] percent ([*]%) of Net Revenue, [*]. Licensee shall not [*] to [*] for the purpose of [*].
8.2 For each unit of a Licensee Chip developed under the 2003 Technology Schedule and made commercially available prior to the Effective Date of this Technology Schedule (the “2003 Licensee Chip(s)”) that ship on or after July 1, 2010, the royalty paid for each 2003 Licensee Chip shall be [*] percent ([*]%) of Net Revenue [*].
If a 2003 Licensee Chip is shipped as a part of a board or sub-system or multi-chip module the royalty for such 2003 Licensee Chip shall be calculated [*]. Notwithstanding the foregoing, in the event that a Licensee Chip [*], the royalty for each unit of a Licensee Chip shall be the [*] percent ([*]%) of Net Revenue, [*]. Licensee shall not [*] to [*] for the purpose of [*].
9. Maintenance Fees: Licensee shall pay MIPS a nonrefundable annual maintenance fee of US$[*] for each twelve (12) month period commencing on the Schedule Effective Date, which fee shall be due and payable for the first year upon execution of this Technology Schedule and for each subsequent year fifteen (15) days prior to each anniversary of the Schedule Effective Date. Licensee shall provide MIPS with the requisite purchase order in the amount of said maintenance fee as soon as practicable after execution of this Technology Schedule and thereafter at least thirty (30) days prior to each applicable payment due date. Licensee’s failure to pay the annual maintenance fee shall not constitute a material breach of the Master Agreement or this Technology Schedule.
10. Maintenance Services: Provided that Licensee has paid each maintenance fee referred to in Section 9 above, MIPS will provide updates and bug fixes made generally available by MIPS to licensees of the Licensed Technology in connection with the MIPS Deliverables during the applicable twelve (12) month periods. At MIPS’ sole discretion, a limited number of updates and/or bug fixes may
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MIPS Confidential
Certain confidential information contained in this document, marked by brackets, has been omitted and filed separately with the Securities and Exchange Commission pursuant to Rule 24b-2 of the Securities Exchange Act of 1934, as amended.
be distributed prior to general availability in order to assure the quality and applicability of the update and/or bug fix.
11. Term: The term of this Technology Schedule shall begin on the Schedule Effective Date and, unless earlier terminated, shall continue for a period of sixteen (16) years. Provided Licensee is not in breach of its obligations under this Technology Schedule and the Master Agreement, Licensee may, but will not be obligated to, renew this Technology Schedule for an additional [*] term upon payment of the then-current license fee, which fee shall not exceed [*] dollars ($[*]).
For purposes of this Technology Schedule, the parties agree that notwithstanding anything in Section 14.4 of the Master Agreement to the contrary, provided Licensee is not in breach of the Agreement or of this Technology Schedule and continues to pay royalties as specified herein, and provided further that the surviving license rights set forth in Section 14.4 and 14.7 of the Master Agreement have not [*], Licensee shall also have the rights set forth in Section 2.1.1 through 2.1.4 of the Master Agreement with respect to any Licensee Chip [*] at the time [*] (a Licensee Chip shall be [*] if Licensee has given MIPS notice at or before the time [*] that said Licensee Chip has [*]) for up to [*] the date of termination or expiration of this Technology Schedule, and thereafter only if Licensee certifies in a writing by a duly authorized officer within said [*] period that the Licensee Chip has been [*] and the [*] has been delivered to an Authorized Foundry for silicon production. The [*] shall then continue with respect to a Licensee Chip for an additional [*] period only if silicon production actually occurs, and thereafter only if Licensee certifies in a writing by a duly authorized officer within said [*] period that silicon production of the Licensee Chip has commenced using a mask set dedicated to Licensee only. If Licensee commercializes a Licensee Chip for which rights survived as provided herein, then provided Licensee is not in breach of the Agreement or of this Technology Schedule and continues to pay royalties as specified herein, Licensee shall have the right to continue having manufactured, distributing and selling such Licensee Chip after the date of termination or expiration of this Technology Schedule.
12. Program Managers:
| For Licensee: | Anil Jain | |
| Corporate VP of IC Engineering | ||
| 100 Nickerson Road | ||
| Marlboro, MA 01752 | ||
| Telephone: 508-683-8815 | ||
| Facsimile: 508-683-8809 | ||
| Email: anil.jain@cavium.com | ||
| For MIPS: | Jess Herrera | |
| Director Sales | ||
| 955 East Arques Ave | ||
| Sunnyvale, CA 94085 | ||
| Telephone: 408-530-7022 | ||
| Facsimile: 408-530-5158 | ||
| Email: jessh@mips.com | ||
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MIPS Confidential
Certain confidential information contained in this document, marked by brackets, has been omitted and filed separately with the Securities and Exchange Commission pursuant to Rule 24b-2 of the Securities Exchange Act of 1934, as amended.
Notice of changes in the above addresses or contacts shall be given in writing in accordance with Section 15.1 of the Master Agreement or by email to the other party’s Program Manager.
13. Licensed Marks: In accordance with the rights granted in the Trademark License Agreement, Licensee may use the following Licensed Marks in connection with the Licensee Chips being developed in accordance with the rights granted in the Master Agreement and this Technology Schedule:
| Licensed Mark |
Exclusive? | Sublicensable? | ||
| MIPS |
No | No | ||
| MIPS32 |
No | No | ||
| MIPS64 |
No | No | ||
| MIPS-Based |
No | No | ||
| MIPS-Verified |
No | No | ||
| CorExtend |
No | No | ||
| M14Kc |
No | No | ||
| M14K |
No | No | ||
| 24KEc |
No | No | ||
| 24KEf |
No | No | ||
| 34Kc |
No | No | ||
| 34Kf |
No | No | ||
| 1004Kc |
No | No | ||
| 1004Kf |
No | No | ||
| 74Kc |
No | No | ||
| 74Kf |
No | No | ||
| SOC-it |
No | No | ||
| cnMIPS |
Yes | No |
14. Press Announcement and Promotion of Licensed Technology: MIPS may announce the existence of the license of the Licensed Technology to Licensee promptly after execution of this Technology Schedule provided that MIPS obtains Licensee’s written consent to such announcement which will not be unreasonably withheld. In the event such press release is a mutual press release MIPS and Licensee will mutually agree to the contents.
15. Additional Terms:
15.1 Export Information: As of the Schedule Effective Date, the Licensed Technology licensed under this Technology Schedule is classified as 3E991, pursuant to the rules and regulations of the U.S. Bureau of Industry and Security (BIS) and may require an export license to reexport this technology or products derived therefrom to certain countries, individuals or entities or for certain prohibited or restricted end uses. Licensee hereby acknowledges and agrees that without an export license or license exception granted by the BIS, Licensee will not: (1) Reexport or otherwise redistribute or release the technology licensed under this Technology Schedule or any MIPS Confidential Information provided under this Technology Schedule to a national of a country in the controlled or embargoed Country Groups (as defined under BIS regulations) applicable to this classification; or (2) Export any derivative product or portions thereof (collectively, “Derivative Product”) of the technology
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MIPS Confidential
Certain confidential information contained in this document, marked by brackets, has been omitted and filed separately with the Securities and Exchange Commission pursuant to Rule 24b-2 of the Securities Exchange Act of 1934, as amended.
licensed under this Technology Schedule to a country in the controlled or embargoed Country Groups applicable to this classification, if such Derivative Product is subject to national security controls as identified on the Commerce Control List (“CCL”) (as defined under BIS regulations) or subject to State Department controls under the United States Munitions List (USML) found in the International Traffic in Arms Regulations (“ITAR”); or (3) knowingly, directly or indirectly, transfer any technology licensed under this Technology Schedule or any MIPS Confidential Information provided under this Technology Schedule or any Licensee product derived from the MIPS Deliverable(s) or any MIPS Confidential Information to any BIS prohibited individual or entity or to any party whose anticipated end use for the information is a prohibited or restricted end use. Specific information may be found at www.bis.doc.gov, and the ITAR, including the USML, may be found at www.pmdtc.org. Such websites and regulations therein may change from time to time as determined by the BIS and Licensee is responsible for complying with the most current regulations. This section shall survive any termination or expiration of this Technology Schedule.
15.2 Approved Licensee Sites: MIPS confirms that the following sites of Licensee are approved sites in which Licensee may use the MIPS Deliverables (including Restricted Confidential Deliverables as provided in Section 10.2 of the Master Agreement):
Cavium Networks
805 East Middlefield Road
Mountain View, CA 94043
Cavium Networks
4F, No.52, Lane 10, Kee Hu Road
Nei Hu Taipei, 11492, Taiwan, R.O.C.
Cavium Networks
Connected Home & Office Group
4F,No.1,Chin-Shan 8th St.
Hsin-Chu 30080 ,Taiwan,R.O.C
Cavium Networks
100 Nickerson Road
Marlborough, MA 01752
Upon Licensee’s notice to MIPS, Licensee may add any research and development site of Licensee within the United States. Upon Licensee’s request and MIPS’ approval, Licensee may obtain additional approved Licensee sites under this Paragraph 15.2. In the event that MIPS approves the use of a third party under Section 2.1 of the Master Agreement, such third party’s site shall be an additional approved site for purposes of Section 10.2 of the Master Agreement, subject to the provisions of Section 2.5 of the Master Agreement.
15.3 Transfer Fee: [*]. Notwithstanding any terms of the Master Agreement to the contrary, this Technology Schedule may not be assigned to any third party unless and until all royalties and other
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Certain confidential information contained in this document, marked by brackets, has been omitted and filed separately with the Securities and Exchange Commission pursuant to Rule 24b-2 of the Securities Exchange Act of 1934, as amended.
payments due and payable prior to the date of the assignment under Paragraphs 7, 8, 9, and 11 above have been paid in full to MIPS.
15.4 MIPS Approvals: MIPS agrees that any approvals or consents to be given by MIPS under the terms of the Master Agreement and this Technology Schedule shall not be unreasonably delayed or withheld. Licensee acknowledges and agrees that approval would not be unreasonably delayed or withheld where consent is requested that involves a competitor of MIPS or MIPS has legitimate concerns about the ability to protect the confidentiality of the Licensed Technology or to enforce MIPS’ Intellectual Property Rights in the jurisdiction involved. MIPS agrees to work with Licensee and any third party acquiror that is a competitor of MIPS that otherwise meets all the requirements in Section 15.5 of the Master Agreement in good faith to mutually agree upon adequate protection mechanisms, and if such agreed upon protection measures are implemented, then MIPS will not deny consent because such party is a competitor of MIPS. MIPS agrees to respond within 30 days of relevant notifications.
15.5 Rights to Modify the Licensed MIPS Architecture: Licensee may not subset, superset or otherwise modify the functional behavior of the Licensed MIPS Architecture except as set forth in Exhibit A to this Technology Schedule. The MIPS64 Architecture based Licensee Chips [*] in accordance with the terms and conditions of the Master Agreement on or before the Schedule Effective Date, or [*] in accordance with the terms and conditions of the Master Agreement after the Schedule Effective Date, are approved by MIPS as MIPS compliant as set forth [*]. Section 2.2 of the Master Agreement provides that except as expressly permitted in the Technology Schedule for the applicable Licensed MIPS Architecture, Licensee may not subset, superset or otherwise modify the functional behavior of the Licensed MIPS Architecture. Exhibit A of the Technology Schedule sets forth Licensees rights to modify the Licensed MIPS Architecture. Based on discussions between the parties, we understand that Licensee may [*]. Notwithstanding anything in Exhibit A of the Technology Schedule to the contrary, MIPS is willing to allow such use, provided Licensee provides MIPS with notice of which Licensee Chips are being developed [*] of the Licensee Chips and the Licensee Chips pass the Compatibility Verification Process set forth in the Master Agreement. Licensee is encouraged to disclose to MIPS and consult with MIPS regarding the [*]. Licensee understands and acknowledges that the decision to use these [*] will require [*], which changes are the sole responsibility of the Licensee.
15.6 Rights to Modify the Licensed MIPS Cores. The 34Kc Core and the 34Kf Core being licensed pursuant to this Technology Schedule includes an option for Licensee to develop enhancements in the Licensee modifiable blocks described in the Implementor’s Guide for such Licensed MIPS Core (“Enhancements”) and certain Licensed MIPS Cores being licensed pursuant to this Technology Schedule include an option for User Defined Instructions (“UDIs”). In the event Licensee desires to develop and/or incorporate any such Enhancements or UDIs in the Licensed MIPS Core utilizing such option, MIPS agrees that notwithstanding any provisions that may be to the contrary in Section 2.4 of the Master Agreement, Licensee may modify and create derivative works of the Licensed MIPS Core solely for such purpose and solely to the extent necessary to incorporate and implement such Enhancements under the license grant in Section 2.3 of the Master Agreement, provided that Licensee understands and agrees that MIPS has the right to itself also develop the same or similar enhancements and implement them in MIPS Technology (including MIPS Architecture and MIPS Cores), which
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MIPS Confidential
Certain confidential information contained in this document, marked by brackets, has been omitted and filed separately with the Securities and Exchange Commission pursuant to Rule 24b-2 of the Securities Exchange Act of 1934, as amended.
architectures and cores may be licensed by MIPS to third parties. Therefore, Licensee hereby agrees that in the event Licensee utilizes such option for Enhancements or UDIs, Licensee and its affiliates will not enforce or assert their Intellectual Property Rights in any modifications or derivative works of the Licensed MIPS Core resulting from such utilization in the same manner as set forth in Section 8.1 as written in the Master Agreement. This paragraph shall survive any expiration or termination of this Technology Schedule.
15.7 Limitations on L2Cache: Notwithstanding anything in the Master Agreement or this Technology Schedule to the contrary, the L2Cache is licensed for use only in Licensee Chips which also incorporate a MIPS32 or MIPS64 core licensed from MIPS or a core developed by Licensee under a separate license with MIPS and is licensed to Licensee without indemnity of any kind (including under Section 12.1 of the Master Agreement).
MIPS agrees that notwithstanding [*], Licensee may [*] solely for [*], provided that Licensee [*]. Therefore, Licensee hereby agrees that in the event Licensee [*], Licensee and its affiliates will not [*]. This paragraph shall survive any expiration or termination of this Technology Schedule.
Licensee agrees at MIPS’ request to provide MIPS under a separate written agreement mutually signed by the parties, [*].
15.8 Notification: Licensee can access the open source simulator at www.mips.com/simulator.
IN WITNESS WHEREOF, each party has caused this Technology Schedule to be executed by its duly authorized representative:
| MIPS TECHNOLOGIES, INC. (“MIPS”)
|
CAVIUM NETWORKS, INC. (“LICENSEE”)
| |||||||
| By: |
|
By: |
| |||||
| Print Name: |
|
Print Name: |
| |||||
| Title: |
|
Title: |
| |||||
| Date: |
|
Date: |
| |||||
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MIPS Confidential
Certain confidential information contained in this document, marked by brackets, has been omitted and filed separately with the Securities and Exchange Commission pursuant to Rule 24b-2 of the Securities Exchange Act of 1934, as amended.
EXHIBIT A
Compliance and Subsetting
To be compliant with the MIPS64 Architecture, designs must implement a set of required features, as described in this section. To allow flexibility in implementations, the MIPS64 Architecture does provide subsetting rules. An implementation that follows these rules is compliant with the MIPS64 Architecture as long as it adheres strictly to the rules, and fully implements the remaining instructions. Supersetting of the MIPS64 Architecture is only allowed by adding functions to the SPECIAL2 major opcode, by adding control for co-processors via the COP2, LWC2, SWC2, LDC2, and/or SDC2, opcodes, or via the addition of MIPS-approved Application Specific Extensions.
[*] is explicitly prohibited by the Architecture unless [*] are approved by MIPS Technologies, Inc., and [*]. For example, modification of the [*] is explicitly prohibited if that mode is intended to be used for production use. Alternate modes intended for non-production use such as testing are excluded from this restriction. This requirement is intended to avoid the creation of new de-facto standards around the MIPS Architecture that are not approved extensions.
The instruction set subsetting rules are as follows:
| • | All CPU instructions must be implemented - no subsetting is allowed. |
| • | The FPU and related support instructions, including the MOVF and MOVT CPU instructions, may be omitted. Software may determine if an FPU is implemented by checking the state of the FP bit in the Config1 CP0 register. If the FPU is implemented, it must include S, D, and W formats, operate instructions, and all supporting instructions. If the FPU is implemented, the paired single (PS) format is optional. Software may determine which FPU data types are implemented by checking the appropriate bit in the FIR CP1 register. The following allowable FPU subsets are compliant with the MIPS64 architecture: |
| • | No FPU |
| • | FPU with S, D, and W, and L formats and all supporting instructions |
| • | FPU with S, D, PS, W, and L formats and all supporting instructions |
| • | Coprocessor 2 is optional and may be omitted. Software may determine if Coprocessor 2 is implemented by checking the state of the C2 bit in the Config1 CP0 register. If Coprocessor 2 is implemented, the Coprocessor 2 interface instructions (BC2, CFC2, COP2, CTC2, DMFC2, DMTC2, LDC2, LWC2, MFC2, MTC2, SDC2, and SWC2) may be omitted on an instruction-by-instruction basis. |
| • | Implementation of the full 64-bit address space is optional. The processor may implement 64-bit data and operations with a 32-bit only address space. In this |
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MIPS Confidential
Certain confidential information contained in this document, marked by brackets, has been omitted and filed separately with the Securities and Exchange Commission pursuant to Rule 24b-2 of the Securities Exchange Act of 1934, as amended.
| case, the MMU acts as if 64-bit addressing is always disabled. Software may determine if the processor implements a 32-bit or 64-bit address space by checking the AT field in the Config CP0 register. |
| • | Supervisor Mode is optional. If Supervisor Mode is not implemented, bit 3 of the Status register must be ignored on write and read as zero. |
| • | The standard TLB-based memory management unit may be replaced with a simpler MMU (e.g., a Fixed Mapping MMU). If this is done, the rest of the interface to the Privileged Resource Architecture must be preserved. If a TLB-based memory management unit is implemented, it must be the standard TLB-based MMU as described in the Privileged Resource Architecture. Software may determine the type of the MMU by checking the MT field in the Config CP0 register. |
| • | The Privileged Resource Architecture includes several implementation options and may be subsetted in accordance with those options. |
| • | Instruction, CP0 Register, and CP1 Control Register fields that are marked “Reserved” or shown as “0” in the description of that field are reserved for future use by the architecture and are not available to implementations. Implementations may only use those fields that are explicitly reserved for implementation dependent use. |
| • | MIPS-approved ASEs are optional and may be subsetted out. If most cases, software may determine if a supported ASE is implemented by checking the appropriate bit in the specified CP0 register(s). If they are implemented, they must implement the entire architecture applicable to the component, or implement subsets that are approved by the ASE specifications. |
| • | EJTAG is optional and may be subsetted out. If it is implemented, it must implement only those subsets that are approved by the EJTAG specification. |
| • | If any instruction is subsetted out based on the rules above, an attempt to execute that instruction must cause the appropriate exception (typically Reserved Instruction or Coprocessor Unusable). |
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Certain confidential information contained in this document, marked by brackets, has been omitted and filed separately with the Securities and Exchange Commission pursuant to Rule 24b-2 of the Securities Exchange Act of 1934, as amended.
EXHIBIT B
MIPS DELIVERABLES
1. Licensed MIPS Architecture: MIPS64® Architecture
Release Control Number: MIPS64ARCH07240601-1.0.0
MIPS Deliverables: (including the confidentiality level and delivery schedule for each Deliverable):
The deliverables are provided electronically as a bundle
| Deliverables |
Document or Part Number |
Restricted Confidential |
Internal Confidential |
External Confidential |
Commercial | Delivery Schedule* | ||||||
| Specifications | ||||||||||||
| MIPS64 Architecture Reference Manual Volume I: Introduction to the MIPS64 Architecture
|
MD00081 | Ö | Within 2 weeks of signing agreement | |||||||||
| MIPS64 Architecture Reference Manual Volume II: The MIPS64 Instruction Set
|
MD00085 | Ö | Within 2 weeks of signing agreement | |||||||||
| MIPS64 Architecture Reference Manual Volume III: The MIPS64 Privileged Resource Architecture
|
MD00089 | Ö | Within 2 weeks of signing agreement | |||||||||
| EJTAG Specification
|
MD00047 | Ö | Within 2 weeks of signing agreement | |||||||||
| PDtrace™ Interface and Trace Control Block Specification
|
MD00439 | Ö | Within 2 weeks of signing agreement | |||||||||
| Verification Suite | ||||||||||||
| MIPS Architecture Verification Programs AVP Environment
|
PN00001 | Ö | Within 2 weeks of signing agreement |
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Certain confidential information contained in this document, marked by brackets, has been omitted and filed separately with the Securities and Exchange Commission pursuant to Rule 24b-2 of the Securities Exchange Act of 1934, as amended.
| Deliverables |
Document or Part Number |
Restricted Confidential |
Internal Confidential |
External Confidential |
Commercial | Delivery Schedule* | ||||||
| MIPS Architecture Verification Programs MIPS32 AVPs
|
PN00002 | Ö | Within 2 weeks of signing agreement | |||||||||
| MIPS Architecture Verification Programs MIPS64 AVPs
|
PN00003 | Ö | Within 2 weeks of signing agreement | |||||||||
| MIPS Architecture Verification Programs Release Notes
|
MD00120 | Ö | Within 2 weeks of signing agreement | |||||||||
| Documentation | ||||||||||||
| MIPS64 Architecture for Programmers Volume I: Introduction to the MIPS64 Architecture
|
MD00083 | Ö | Within 2 weeks of signing agreement | |||||||||
| MIPS64™ Architecture for Programmers Volume II: The MIPS64™ Instruction Set
|
MD00087 | Ö | Within 2 weeks of signing agreement | |||||||||
| MIPS64™ Architecture for Programmers Volume III: The MIPS64™ Privileged Resource Architecture
|
MD00091 | Ö | Within 2 weeks of signing agreement |
| * | Delivery Date is subject to the conditions set forth in Section 2 of this Technology Schedule. |
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Certain confidential information contained in this document, marked by brackets, has been omitted and filed separately with the Securities and Exchange Commission pursuant to Rule 24b-2 of the Securities Exchange Act of 1934, as amended.
1. Licensed MIPS® Core: MIPS32® M14Kc™ Synthesizable Processor Core
2. MIPS32 M14Kc Core Deliverables (including the confidentiality level for each MIPS Deliverable):
Release Control Number M14Kc-20100325-1.3.0
The MIPS32® M14Kc™ Deliverables are provided electronically as a bundle.
The confidentiality level and delivery schedule for each item is listed below.
| Deliverable |
Document or Part Number |
Restricted Confidential |
Internal Confidential |
External Confidential |
Commercial | Delivery Date* | ||||||
| Documentation | ||||||||||||
| MIPS32 M14Kc Datasheet |
MD00672 | Ö | Within 2 weeks of signing agreement | |||||||||
| MIPS32 M14Kc Processor Core Release Notes |
MD00677 | Ö | Within 2 weeks of signing agreement | |||||||||
| MIPS32 M14Kc Processor Core RTL Errata Sheet |
MD00676 | Ö | Within 2 weeks of signing agreement | |||||||||
| MIPS32 M14Kc Processor Known Issues |
MD00720 | Ö | Within 2 weeks of signing agreement | |||||||||
| MIPS32 M14Kc Processor Core Implementer’s Guide |
MD00675 | Ö | Within 2 weeks of signing agreement | |||||||||
| MIPS32 M14Kc Processor Core Integrator’s Guide |
MD00673 | Ö | Within 2 weeks of signing agreement | |||||||||
| MIPS32 M14Kc Processor Core Software User’s Manual |
MD00674 | Ö | Within 2 weeks of signing agreement | |||||||||
| MIPS32 M14Kc Processor Core System User’s Manual |
MD00718 | Ö | Within 2 weeks of signing agreement | |||||||||
| MIPS EJTAG Specification |
MD00047 | Ö | Within 2 weeks of signing agreement | |||||||||
| EJTAG Implementation Application Note |
MD00071 | Ö | Within 2 weeks of signing agreement | |||||||||
| MIPS iFlowtrace™ Architecture Specification |
MD00526 | Ö | Within 2 weeks of signing agreement | |||||||||
| Core Coprocessor Interface Specification |
MD00068 | Ö | Within 2 weeks of signing agreement | |||||||||
| Core Coprocessor 2 Module Template Application Note |
MD00130 | Ö | Within 2 weeks of signing agreement | |||||||||
| Cache Configuration Application Note |
MD00213 | Ö | Within 2 weeks of signing agreement | |||||||||
13
MIPS Confidential
Certain confidential information contained in this document, marked by brackets, has been omitted and filed separately with the Securities and Exchange Commission pursuant to Rule 24b-2 of the Securities Exchange Act of 1934, as amended.
| Deliverable |
Document or Part Number |
Restricted Confidential |
Internal Confidential |
External Confidential |
Commercial | Delivery Date* | ||||||
| Converting ELF files for Verilog Simulation – ELFVIEW Application Note |
MD00338 | Ö | Within 2 weeks of signing agreement | |||||||||
| MIPS Architecture For Programmers Volume I-A: Introduction to the MIPS32 Architecture |
MD00082 | Ö | Within 2 weeks of signing agreement | |||||||||
| MIPS Architecture For Programmers Volume I-B: Introduction to the microMIPS32™ Architecture |
MD00741 | Ö | Within 2 weeks of signing agreement | |||||||||
| MIPS Architecture For Programmers Volume II-A: The MIPS32 Instruction Set |
MD00086 | Ö | Within 2 weeks of signing agreement | |||||||||
| MIPS Architecture For Programmers Volume II-B: The microMIPS32 Instruction Set |
MD00582 | Ö | Within 2 weeks of signing agreement | |||||||||
| MIPS Architecture For Programmers Volume III: The MIPS32 and microMIPS32 Privileged Resource Architecture |
MD00090 | Ö | Within 2 weeks of signing agreement | |||||||||
| MIPS Architecture For Programmers Volume IV-h: MCU Application-Specific Extension to the MIPS32 and microMIPS32 Architectures |
MD00641 | Ö | Within 2 weeks of signing agreement | |||||||||
| Mini Testbench Specification |
MD00493 | Ö | Within 2 weeks of signing agreement | |||||||||
| MIPS Physical Design Guide |
MD00606 | Ö | Within 2 weeks of signing agreement | |||||||||
| MIPS Architecture Verification Programs Release Notes |
MD00120 | Ö | Within 2 weeks of signing agreement | |||||||||
| MIPS Architecture Verification Programs User Manual |
MD00121 | Ö | Within 2 weeks of signing agreement | |||||||||
| MIPS Architecture Verification Programs Errata Sheet |
MD00142 | Ö | Within 2 weeks of signing agreement | |||||||||
|
CorExtend® Instructions Integrator’s Guide for M4K/4KE/4KS/M14K/M14Kc |
MD00324 | Ö | Within 2 weeks of signing agreement | |||||||||
|
Accelerating VoIP with CorExtend in MIPS32 Pro Series |
MD00302 | Ö | Within 2 weeks of signing agreement | |||||||||
| Accelerating DSP Filter Loops with CorExtend in MIPS32 Pro Series Cores |
MD00303 | Ö | Within 2 weeks of signing agreement |
14
MIPS Confidential
Certain confidential information contained in this document, marked by brackets, has been omitted and filed separately with the Securities and Exchange Commission pursuant to Rule 24b-2 of the Securities Exchange Act of 1934, as amended.
| Deliverable |
Document or Part Number |
Restricted Confidential |
Internal Confidential |
External Confidential |
Commercial | Delivery Date* | ||||||
| Design Data | ||||||||||||
| Verilog RTL for M14Kc Core |
Ö | Within 2 weeks of signing agreement | ||||||||||
| Configuration Tools | ||||||||||||
|
Configuration GUI tool |
Ö | Within 2 weeks of signing agreement | ||||||||||
|
Configuration GUI support for CorExtend UDI |
Ö | Within 2 weeks of signing agreement | ||||||||||
| Synthesis Support | ||||||||||||
| Reference flow scripts for Synopsys tools |
Ö1 | Within 2 weeks of signing agreement | ||||||||||
| Reference flow scripts for Cadence tools |
Ö1 | Within 2 weeks of signing agreement | ||||||||||
| Reference flow scripts for Magma tools |
Ö1 | Within 2 weeks of signing agreement | ||||||||||
| Simulation Models | ||||||||||||
| MIPS32 M14Kc Cycle-exact simulation model (VMC) |
Ö2,3,4 | Within 2 weeks of signing agreement | ||||||||||
| Simulation Support | ||||||||||||
| Build and run scripts for M14Kc Core |
Ö1 | Within 2 weeks of signing agreement | ||||||||||
| Simulation and verification test bench RTL |
Ö | Within 2 weeks of signing agreement | ||||||||||
| Verification Suite | ||||||||||||
| Memory image for M14Kc Core diagnostics |
Ö | Within 2 weeks of signing agreement | ||||||||||
| DFT Support – Tools | ||||||||||||
| Mentor – DFTAdvisor and FastScan scripts |
Ö1 | Within 2 weeks of signing agreement | ||||||||||
| Synopsys – DFT Compiler and TetraMAX scripts |
Ö1 | Within 2 weeks of signing agreement | ||||||||||
| Timing Analysis | ||||||||||||
| Reference STA scripts for Synopsys PrimeTime tools |
Ö1 | Within 2 weeks of signing agreement | ||||||||||
| Power Analysis | ||||||||||||
| Synopsys PrimeTime-PX scripts |
Ö1 | Within 2 weeks of signing agreement | ||||||||||
| 1 | Licensee may modify as necessary to support chip development. |
| 2 | Licensee’s customer may not modify or distribute. |
| 3 | The VMC model is supported on RedHat Linux only. |
| 4 | The VMC model is managed with FLEXlm license keys and Licensee shall be provided upon request with up to 40 keys. Additional keys for the VMC model are available upon request at the then-current license fees. |
| * | Delivery Date is subject to the conditions set forth in Section 2 of this Technology Schedule. |
15
MIPS Confidential
Certain confidential information contained in this document, marked by brackets, has been omitted and filed separately with the Securities and Exchange Commission pursuant to Rule 24b-2 of the Securities Exchange Act of 1934, as amended.
The CASim™ Cycle Accurate Simulator for the MIPS32 M14Kc Core Deliverables
| Deliverable | Document or Part Number |
Restricted Confidential |
Internal Confidential |
External Confidential |
Commercial | Delivery Date* | ||||||
| Cycle Accurate Simulator | ||||||||||||
| CASim Cycle Accurate Simulator for the MIPS32 M14Kc Core for Red Hat Linux |
PN00226 | Ö1 | Within 2 weeks of signing agreement | |||||||||
| CASim Cycle Accurate Simulator for the MIPS32 M14Kc Core for Microsoft Windows |
PN00224 | Ö1 | Within 2 weeks of signing agreement | |||||||||
| Documentation | ||||||||||||
| CASim Cycle Accurate Simulator for M14Kc Release Notes |
MD00715 | Ö | Within 2 weeks of signing agreement | |||||||||
| CASim Cycle Accurate Simulator for M14Kc User Guide |
MD00699 | Ö2 | Within 2 weeks of signing agreement | |||||||||
| 1 | The CASim Deliverables are managed with FLEXlm license keys and Licensee shall be provided upon request with up to 10 keys. Additional keys for CASim are available upon request at the then-current license fees. |
| 2 | Licensee’s customer may not modify or distribute. |
| * | Delivery Date is subject to the conditions set forth in Section 2 of this Technology Schedule. |
16
MIPS Confidential
Certain confidential information contained in this document, marked by brackets, has been omitted and filed separately with the Securities and Exchange Commission pursuant to Rule 24b-2 of the Securities Exchange Act of 1934, as amended.
The MIPS BFM Deliverables are provided electronically as a bundle:
| Deliverable | Document or Part Number |
Restricted Confidential |
Internal Confidential |
External Confidential |
Commercial | Delivery Date* | ||||||
| Bus Functional Model | ||||||||||||
| Bus Functional Model for the MIPS32 M14Kc Processor Core for Red Hat Linux |
PN00230 | Ö1 | Within 2 weeks of signing agreement | |||||||||
| Bus Functional Model for the MIPS32 M14Kc Processor Core for Microsoft Windows |
PN00229 | Ö1 | Within 2 weeks of signing agreement | |||||||||
| Documentation | ||||||||||||
| MIPS32 M14Kc Bus Functional Model Release Note
|
MD00730 | Ö | Within 2 weeks of signing agreement | |||||||||
| MIPS32 M14Kc Bus Functional Model Software User’s Manual |
MD00729 | Ö2 | Within 2 weeks of signing agreement | |||||||||
| MIPS32 M14Kc Bus Functional Model Software Integrator’s Guide |
MD00728 | Ö2 | Within 2 weeks of signing agreement | |||||||||
| 1 | The MIPS BFM Deliverables are managed with FLEXlm license keys and Licensee shall be provided upon request with up to 10 keys. Additional keys for the BFM are available upon request at the then-current license fees. |
| 2 | Licensee’s customer may not modify or distribute. |
| * | Delivery Date is subject to the conditions set forth in Section 2 of this Technology Schedule. |
17
MIPS Confidential
Certain confidential information contained in this document, marked by brackets, has been omitted and filed separately with the Securities and Exchange Commission pursuant to Rule 24b-2 of the Securities Exchange Act of 1934, as amended.
1. Licensed MIPS® Core: MIPS32® M14K™ Synthesizable Processor Core
2. MIPS32 M14K Core Deliverables (including the confidentiality level for each MIPS Deliverable):
Release Control Number M14K-20100325-1.3.0
The MIPS32® M14K™ Deliverables are provided electronically as a bundle.
The confidentiality level and delivery schedule for each item is listed below.
| Deliverable | Document or Part Number |
Restricted Confidential |
Internal Confidential |
External Confidential |
Commercial | Delivery Date* | ||||||
| Documentation | ||||||||||||
| MIPS32 M14K Datasheet |
MD00666 | Ö | Within 2 weeks of signing agreement | |||||||||
| MIPS32 M14K Processor Core Release Notes |
MD00671 | Ö | Within 2 weeks of signing agreement | |||||||||
| MIPS32 M14K Processor Core RTL Errata Sheet |
MD00670 | Ö | Within 2 weeks of signing agreement | |||||||||
| MIPS32 M14K Processor Known Issues |
MD00719 | Ö | Within 2 weeks of signing agreement | |||||||||
| MIPS32 M14K Processor Core Implementer’s Guide |
MD00669 | Ö | Within 2 weeks of signing agreement | |||||||||
| MIPS32 M14K Processor Core Integrator’s Guide |
MD00667 | Ö | Within 2 weeks of signing agreement | |||||||||
| MIPS32 M14K Processor Core Software User’s Manual |
MD00668 | Ö | Within 2 weeks of signing agreement | |||||||||
| MIPS32 M14K Processor Core System User’s Manual |
MD00717 | Ö | Within 2 weeks of signing agreement | |||||||||
| MIPS EJTAG Specification |
MD00047 | Ö | Within 2 weeks of signing agreement | |||||||||
| EJTAG Implementation Application Note |
MD00071 | Ö | Within 2 weeks of signing agreement | |||||||||
| MIPS iFlowtrace™ Architecture Specification |
MD00526 | Ö | Within 2 weeks of signing agreement | |||||||||
| Core Coprocessor Interface Specification |
MD00068 | Ö | Within 2 weeks of signing agreement | |||||||||
| Core Coprocessor 2 Module Template Application Note |
MD00130 | Ö | Within 2 weeks of signing agreement | |||||||||
|
Reference Design for MIPS32 M14K Cores Application Note |
MD00716 | Ö | Within 2 weeks of signing agreement | |||||||||
18
MIPS Confidential
Certain confidential information contained in this document, marked by brackets, has been omitted and filed separately with the Securities and Exchange Commission pursuant to Rule 24b-2 of the Securities Exchange Act of 1934, as amended.
| Deliverable | Document or Part Number |
Restricted Confidential |
Internal Confidential |
External Confidential |
Commercial | Delivery Date* | ||||||
|
Converting ELF files for Verilog Simulation – ELFVIEW Application Note |
MD00338 | Ö | Within 2 weeks of signing agreement | |||||||||
| MIPS Architecture For Programmers Volume I-A: Introduction to the MIPS32 Architecture |
MD00082 | Ö | Within 2 weeks of signing agreement | |||||||||
| MIPS Architecture For Programmers Volume I-B: Introduction to the microMIPS32™ Architecture |
MD00741 | Ö | Within 2 weeks of signing agreement | |||||||||
| MIPS Architecture For Programmers Volume II-A: The MIPS32 Instruction Set |
MD00086 | Ö | Within 2 weeks of signing agreement | |||||||||
| MIPS Architecture For Programmers Volume II-B: The microMIPS32 Instruction Set |
MD00582 | Ö | Within 2 weeks of signing agreement | |||||||||
| MIPS Architecture For Programmers Volume III: The MIPS32 and microMIPS32 Privileged Resource Architecture |
MD00090 | Ö | Within 2 weeks of signing agreement | |||||||||
| MIPS Architecture For Programmers Volume IV-h: MCU Application-Specific Extension to the MIPS32 and microMIPS32 Architectures |
MD00641 | Ö | Within 2 weeks of signing agreement | |||||||||
| Mini Testbench Specification |
MD00493 | Ö | Within 2 weeks of signing agreement | |||||||||
| MIPS Physical Design Guide |
MD00606 | Ö | Within 2 weeks of signing agreement | |||||||||
| MIPS Architecture Verification Programs Release Notes |
MD00120 | Ö | Within 2 weeks of signing agreement | |||||||||
| MIPS Architecture Verification Programs User Manual |
MD00121 | Ö | Within 2 weeks of signing agreement | |||||||||
| MIPS Architecture Verification Programs Errata Sheet |
MD00142 | Ö | Within 2 weeks of signing agreement | |||||||||
|
CorExtend® Instruction Integrator’s Guide for M4K/4KE/4KS/M14K/M14Kc |
MD00324 | Ö | Within 2 weeks of signing agreement | |||||||||
|
Accelerating VoIP with CorExtend in MIPS32 Pro Series |
MD00302 | Ö | Within 2 weeks of signing agreement | |||||||||
|
Accelerating DSP Filter Loops with CorExtend in MIPS32 Pro Series Cores |
MD00303 | Ö | Within 2 weeks of signing agreement |
19
MIPS Confidential
Certain confidential information contained in this document, marked by brackets, has been omitted and filed separately with the Securities and Exchange Commission pursuant to Rule 24b-2 of the Securities Exchange Act of 1934, as amended.
| Deliverable | Document or Part Number |
Restricted Confidential |
Internal Confidential |
External Confidential |
Commercial | Delivery Date* | ||||||
| Design Data | ||||||||||||
| Verilog RTL for M14K Core including Reference Design |
Ö | Within 2 weeks of signing agreement | ||||||||||
| Configuration Tools | ||||||||||||
| Configuration GUI tool |
Ö | Within 2 weeks of signing agreement | ||||||||||
|
Configuration GUI support for CorExtend UDI |
Ö | Within 2 weeks of signing agreement | ||||||||||
| Synthesis Support | ||||||||||||
| Reference flow scripts for Synopsys tools |
Ö1 | Within 2 weeks of signing agreement | ||||||||||
| Reference flow scripts for Cadence tools |
Ö1 | Within 2 weeks of signing agreement | ||||||||||
| Reference flow scripts for Magma tools |
Ö1 | Within 2 weeks of signing agreement | ||||||||||
| Simulation Models | ||||||||||||
| MIPS32 M14K Cycle-exact simulation model (VMC) |
Ö2,3,4 | Within 2 weeks of signing agreement | ||||||||||
| Simulation Support | ||||||||||||
| Build and run scripts for M14K Core |
Ö1 | Within 2 weeks of signing agreement | ||||||||||
| Simulation and verification test bench RTL |
Ö | Within 2 weeks of signing agreement | ||||||||||
| Verification Suite | ||||||||||||
| Memory image for M14K Core diagnostics |
Ö | Within 2 weeks of signing agreement | ||||||||||
| DFT Support – Tools | ||||||||||||
| Mentor – DFTAdvisor and FastScan scripts |
Ö1 | Within 2 weeks of signing agreement | ||||||||||
| Synopsys – DFT Compiler and TetraMAX scripts |
Ö1 | Within 2 weeks of signing agreement | ||||||||||
| Timing Analysis | ||||||||||||
| Reference STA scripts for Synopsys PrimeTime tools |
Ö1 | Within 2 weeks of signing agreement | ||||||||||
| Power Analysis | ||||||||||||
| Synopsys PrimeTime-PX scripts |
Ö1 | Within 2 weeks of signing agreement | ||||||||||
| 1 | Licensee may modify as necessary to support chip development. |
| 2 | Licensee’s customer may not modify or distribute. |
| 3 | The VMC model is supported on RedHat Linux only. |
| 4 | The VMC model is managed with FLEXlm license keys and Licensee shall be provided upon request with up to 40 keys. Additional keys for the VMC model are available upon request at the then-current license fees. |
| * | Delivery Date is subject to the conditions set forth in Section 2 of this Technology Schedule. |
20
MIPS Confidential
Certain confidential information contained in this document, marked by brackets, has been omitted and filed separately with the Securities and Exchange Commission pursuant to Rule 24b-2 of the Securities Exchange Act of 1934, as amended.
The CASim™ Cycle Accurate Simulator for the MIPS32 M14K Core Deliverables
| Deliverable | Document or Part Number |
Restricted Confidential |
Internal Confidential |
External Confidential |
Commercial | Delivery Date* | ||||||
| Cycle Accurate Simulator | ||||||||||||
| CASim Cycle Accurate Simulator for the MIPS32 M14K Core for Red Hat Linux |
PN00225 | Ö1 | Within 2 weeks of signing agreement | |||||||||
| CASim Cycle Accurate Simulator for the MIPS32 M14K Core for Microsoft Windows |
PN00223 | Ö1 | Within 2 weeks of signing agreement | |||||||||
| Documentation | ||||||||||||
| CASim Cycle Accurate Simulator for M14K Release Notes |
MD00713 | Ö | Within 2 weeks of signing agreement | |||||||||
| CASim Cycle Accurate Simulator for M14K User Guide |
MD00697 | Ö2 | Within 2 weeks of signing agreement | |||||||||
| 1 | The CASim Deliverables are managed with FLEXlm license keys and Licensee shall be provided upon request with up to 10 keys. Additional keys for CASim are available upon request at the then-current license fees. |
| 2 | Licensee’s customer may not modify or distribute. |
| * | Delivery Date is subject to the conditions set forth in Section 2 of this Technology Schedule. |
| * | Delivery Date is subject to the conditions set forth in Section 2 of this Technology Schedule. |
The MIPS BFM Deliverables are provided electronically as a bundle:
| Deliverable | Document
or Part Number |
Restricted
Confidential |
Internal
Confidential |
External
Confidential |
Commercial | Delivery Date* | ||||||
| Bus Functional Model | ||||||||||||
| Bus Functional Model for the MIPS32 M14K Processor Core for Red Hat Linux |
PN00228 | Ö1 | Within 2 weeks of signing agreement | |||||||||
| Bus Functional Model for the MIPS32 M14K Processor Core for Microsoft Windows |
PN00227 | Ö1 | Within 2 weeks of signing agreement | |||||||||
| Documentation | ||||||||||||
| MIPS32 M14K Bus Functional Model Release Notes |
MD00727 | Ö | Within 2 weeks of signing agreement | |||||||||
21
MIPS Confidential
Certain confidential information contained in this document, marked by brackets, has been omitted and filed separately with the Securities and Exchange Commission pursuant to Rule 24b-2 of the Securities Exchange Act of 1934, as amended.
| Deliverable | Document
or Part Number |
Restricted
Confidential |
Internal
Confidential |
External
Confidential |
Commercial | Delivery Date* | ||||||
| MIPS32 M14K Bus Functional Model Software User’s Manual |
MD00726 | Ö2 | Within 2 weeks of signing agreement | |||||||||
| MIPS32 M14K Bus Functional Model Software Integrator’s Guide |
MD00725 | Ö2 | Within 2 weeks of signing agreement |
| 1 | The MIPS BFM Deliverables are managed with FLEXlm license keys and Licensee shall be provided upon request with up to 10 keys. Additional keys for the BFM are available upon request at the then-current license fees. |
| 2 | Licensee’s customer may not modify or distribute. |
| * | Delivery Date is subject to the conditions set forth in Section 2 of this Technology Schedule. |
22
MIPS Confidential
Certain confidential information contained in this document, marked by brackets, has been omitted and filed separately with the Securities and Exchange Commission pursuant to Rule 24b-2 of the Securities Exchange Act of 1934, as amended.
1. Licensed MIPS Core: MIPS32® 24KEc™ Synthesizable Processor Core
2. MIPS32® 24KEc™ Deliverables (including the confidentiality level and Delivery Schedule for each MIPS Deliverable):
Release Control Number 24KEc031720090202-2.5.1
The MIPS32® 24KEc™ Deliverables are provided electronically as a bundle.
| Deliverable | Document or Part Number |
Restricted Confidential |
Internal Confidential |
External Confidential |
Commercial | Delivery Date* | ||||||
| Documentation | ||||||||||||
| 24KE™ Core Release Notes |
MD00489 | Ö | Within 2 weeks of signing agreement | |||||||||
| 24KE™ Core Known Issues |
MD00490 | Ö | Within 2 weeks of signing agreement | |||||||||
| MIPS32 24K and 24KE Processor Core Family Implementer’s Guide |
MD00347 | Ö | Within 2 weeks of signing agreement | |||||||||
| MIPS32 24K and 24KE Processor Core Family Integrator’s Guide |
MD00344 | Ö | Within 2 weeks of signing agreement | |||||||||
| MIPS32 24KE Processor Core Family Software User’s Manual |
MD00468 | Ö | Within 2 weeks of signing agreement | |||||||||
|
Programming the MIPS32 24KE Core Family |
MD00458 | Ö | Within 2 weeks of signing agreement | |||||||||
| MIPS32 24KE Processor Core Family RTL Errata Sheet |
MD00469 | Ö | Within 2 weeks of signing agreement | |||||||||
| MIPS32 24KEc Processor Core Datasheet |
MD00445 | Ö | Within 2 weeks of signing agreement | |||||||||
| Cache SRAM Excerpt from Implementer’s Guide for MIPS32 24K, 24KE, and 34K Cores |
MD00400 | Ö | Within 2 weeks of signing agreement | |||||||||
|
MIPS® Physical Design Guide |
MD00606 | Ö | Within 2 weeks of signing agreement | |||||||||
| OCP2.2 Compliance Checker for MIPS32® Cores |
MD00596 | Ö | Within 2 weeks of signing agreement | |||||||||
|
MIPS32® 24KE™ Processor Core System Users Manual |
MD00650 | Ö | Within 2 weeks of signing agreement | |||||||||
|
Coprocessor 2 Module Template Application Note for MIPS32 24K and 24KE Cores |
MD00425 | Ö | Within 2 weeks of signing agreement | |||||||||
| Cache Configuration Application Note |
MD00213 | Ö | Within 2 weeks of signing agreement | |||||||||
|
Converting ELF Files for Verilog Simulation - ELFVIEW Application Note |
MD00338 | Ö | Within 2 weeks of signing agreement | |||||||||
23
MIPS Confidential
Certain confidential information contained in this document, marked by brackets, has been omitted and filed separately with the Securities and Exchange Commission pursuant to Rule 24b-2 of the Securities Exchange Act of 1934, as amended.
| Deliverable | Document or Part Number |
Restricted Confidential |
Internal Confidential |
External Confidential |
Commercial | Delivery Date* | ||||||
| EJTAG Specification |
MD00047 | Ö | Within 2 weeks of signing agreement | |||||||||
| EJTAG Implementation Application Note |
MD00071 | Ö | Within 2 weeks of signing agreement | |||||||||
| The PDtrace™ Interface and Trace Control Block Specification |
MD00439 | Ö | Within 2 weeks of signing agreement | |||||||||
| Using PDtrace with SDE and System Navigator for MIPS Cores |
MD00543 | Ö | Within 2 weeks of signing agreement | |||||||||
| Core Coprocessor Interface Specification |
MD00068 | Ö | Within 2 weeks of signing agreement | |||||||||
| MIPS32 Architecture For Programmers Volume I: Introduction to the MIPS32® Architecture |
MD00082 | Ö | Within 2 weeks of signing agreement | |||||||||
| MIPS32 Architecture For Programmers Volume II: The MIPS32 Instruction Set |
MD00086 | Ö | Within 2 weeks of signing agreement | |||||||||
| MIPS32 Architecture For Programmers Volume III: The MIPS32 Privileged Resource Architecture |
MD00090 | Ö | Within 2 weeks of signing agreement | |||||||||
| MIPS32 Architecture For Programmers Volume IV-a: The MIPS16e Application-Specific Extension to the MIPS32 Architecture |
MD00076 | Ö | Within 2 weeks of signing agreement | |||||||||
| MIPS32 Architecture For Programmers Volume IV-e: The MIPS DSP Application-Specific Extension to the MIPS32 Architecture |
MD00374 | Ö | Within 2 weeks of signing agreement | |||||||||
| MINI Testbench Specification |
MD00493 | Ö | Within 2 weeks of signing agreement | |||||||||
|
Effective Programming of the 24KE and the 34K Core Families for DSP Code |
MD00475 | Ö | Within 2 weeks of signing agreement | |||||||||
| JPEG Decoder Optimization for the 24KE™ and the 34K™ Core Families |
MD00483 | Ö | Within 2 weeks of signing agreement | |||||||||
|
Optimizing the ITU-T G.729AB Codec for the MIPS32® 24KE™ and 34K™ Core Families |
MD00484 | Ö | Within 2 weeks of signing agreement | |||||||||
|
Efficient DSP ASE Programming in C: Tips and Tricks |
MD00485 | Ö | Within 2 weeks of signing agreement | |||||||||
| MP3 Decoder Optimization for the 24KE™ and the 34K™ Core Families |
MD00495 | Ö | Within 2 weeks of signing agreement | |||||||||
| H.263 Decoder Optimization for the 24KE™ and the 34K™ Core Families |
MD00533 | Ö | Within 2 weeks of signing agreement |
24
MIPS Confidential
Certain confidential information contained in this document, marked by brackets, has been omitted and filed separately with the Securities and Exchange Commission pursuant to Rule 24b-2 of the Securities Exchange Act of 1934, as amended.
| Deliverable | Document or Part Number |
Restricted Confidential |
Internal Confidential |
External Confidential |
Commercial | Delivery Date* | ||||||
|
Optimizing G.722.2 Speech Codec for the MIPS32® 24KE™ and 34K™ Cores |
MD00551 | Ö | Within 2 weeks of signing agreement | |||||||||
| Working with ScratchPad RAMs for MIPS32® 24K® and 34K™ Cores Application Note |
MD00540 | Ö | Within 2 weeks of signing agreement | |||||||||
| Design Data | ||||||||||||
| Verilog RTL for MIPS32 24KEc Core |
Ö | Within 2 weeks of signing agreement | ||||||||||
| Configuration Tools | ||||||||||||
|
Configuration GUI tool |
Ö | Within 2 weeks of signing agreement | ||||||||||
| Synthesis Support | ||||||||||||
|
Reference flow scripts for Synopsys tools |
Ö1 | Within 2 weeks of signing agreement | ||||||||||
|
Reference flow scripts for Cadence tools |
Ö1 | Within 2 weeks of signing agreement | ||||||||||
|
Reference flow scripts for Magma tools |
Ö1 | Within 2 weeks of signing agreement | ||||||||||
|
Synplicity Synplify Pro – FPGA synthesis scripts |
Ö1 | Within 2 weeks of signing agreement | ||||||||||
| Simulation Models | ||||||||||||
| MIPS32 24KE cycle-exact simulation model (VMC) |
Ö2,3,4 | Within 2 weeks of signing agreement | ||||||||||
| Simulation Support | ||||||||||||
| Build and run scripts |
Ö1 | Within 2 weeks of signing agreement | ||||||||||
|
Simulation and verification test bench RTL |
Ö | Within 2 weeks of signing agreement | ||||||||||
| Verification Suite | ||||||||||||
| Memory image for Core diagnostics |
Ö | Within 2 weeks of signing agreement | ||||||||||
| DFT Support - Tools | ||||||||||||
| Mentor – DFTAdvisor and FastScan scripts |
Ö1 | Within 2 weeks of signing agreement | ||||||||||
25
MIPS Confidential
Certain confidential information contained in this document, marked by brackets, has been omitted and filed separately with the Securities and Exchange Commission pursuant to Rule 24b-2 of the Securities Exchange Act of 1934, as amended.
| Deliverable | Document or Part Number |
Restricted Confidential |
Internal Confidential |
External Confidential |
Commercial | Delivery Date* | ||||||
| Synopsys – DFT Compiler and TetraMAX scripts |
Ö1 | Within 2 weeks of signing agreement | ||||||||||
| Timing Analysis | ||||||||||||
|
Reference STA scripts for Synopsys PrimeTime tools |
Ö1 | Within 2 weeks of signing agreement | ||||||||||
| Power Analysis | ||||||||||||
| Synopsys PrimePower scripts |
Ö1 | Within 2 weeks of signing agreement | ||||||||||
| 1 | Licensee may modify as necessary to support chip development. |
| 2 | Licensee’s customer may not modify or distribute. |
| 3 | The VMC model is supported on Sun-Solaris and x86 RedHat Linux only. |
| 4 | The VMC model is managed with FLEXlm license keys and Licensee shall be provided upon request with up to 40 keys. Additional keys for the VMC model are available upon request at the then-current license fees. |
| * | Delivery Date is subject to the conditions set forth in Section 2 of this Technology Schedule. |
The MIPSsim Deliverables are provided electronically as a bundle:
| Deliverable | Document or Part Number |
Restricted Confidential |
Internal Confidential |
External Confidential |
Commercial | Delivery Date* | ||||||
| Instruction Set Simulator | ||||||||||||
| MIPS32 Instruction Set Simulator for 24KE Processor Core Family for RedHat Linux |
PN00206 | Ö1 | Within 2 weeks of signing agreement | |||||||||
| MIPS32 Instruction Set Simulator for 24KE Processor Core Family for Microsoft Windows |
PN00205 | Ö1 | Within 2 weeks of signing agreement | |||||||||
| Documentation | ||||||||||||
| MIPSsim Software Release Notes for 24KE Cores |
MD00457 | Ö | Within 2 weeks of signing agreement | |||||||||
| MIPSsim Software Getting Started Guide for 24KE Cores |
MD00456 | Ö2 | Within 2 weeks of signing agreement | |||||||||
| MIPSsim Software Integrator’s Guide |
MD00357 | Ö2 | Within 2 weeks of signing agreement | |||||||||
26
MIPS Confidential
Certain confidential information contained in this document, marked by brackets, has been omitted and filed separately with the Securities and Exchange Commission pursuant to Rule 24b-2 of the Securities Exchange Act of 1934, as amended.
| Deliverable | Document or Part Number |
Restricted Confidential |
Internal Confidential |
External Confidential |
Commercial | Delivery Date* | ||||||
|
Microprocessor Debug Interface (MDI) Specification |
MD00412 | Ö | Within 2 weeks of signing agreement |
| 1 | The MIPSsim Deliverables are managed with FLEXlm license keys and Licensee shall be provided upon request with up to 10 keys. Additional keys for MIPSsim are available upon request at the then-current license fees. |
| 2 | Licensee’s customer may not modify or distribute. |
| * | Delivery Date is subject to the conditions set forth in Section 2 of this Technology Schedule. |
The MIPS BFM Deliverables are provided electronically as a bundle:
| Deliverable | Document
or Part Number |
Restricted Confidential |
Internal Confidential |
External Confidential |
Commercial | Delivery Date* | ||||||
| Bus Functional Model | ||||||||||||
| Bus Functional Model for the MIPS32 24KE Processor Core Family for RedHat Linux |
PN00100 | Ö1 | Within 2 weeks of signing agreement | |||||||||
| Bus Functional Model for the MIPS32 24KE Processor Core Family for Microsoft Windows |
PN00099 | Ö1 | Within 2 weeks of signing agreement | |||||||||
| Documentation | ||||||||||||
| MIPS32 24KE Bus Functional Model Release Notes |
MD00461 | Ö | Within 2 weeks of signing agreement | |||||||||
| MIPS32 24KE Bus Functional Model Software User’s Manual |
MD00459 | Ö2 | Within 2 weeks of signing agreement | |||||||||
| MIPS32 24KE Bus Functional Model Integrator’s Guide |
MD00460 | Ö2 | Within 2 weeks of signing agreement | |||||||||
|
Debugging an Integrated MIPSsim and MIPS BFM |
MD00381 | Ö2 | Within 2 weeks of signing agreement | |||||||||
| 1 | The MIPS BFM Deliverables are managed with FLEXlm license keys and Licensee shall be provided upon request with up to 10 keys. Additional keys for the BFM are available upon request at the then-current license fees. |
| 2 | Licensee’s customer may not modify or distribute. |
| * | Delivery Date is subject to the conditions set forth in Section 2 of this Technology Schedule. |
27
MIPS Confidential
Certain confidential information contained in this document, marked by brackets, has been omitted and filed separately with the Securities and Exchange Commission pursuant to Rule 24b-2 of the Securities Exchange Act of 1934, as amended.
1. Licensed MIPS Core: MIPS32® 24KEf™ Synthesizable Processor Core
2. MIPS32® 24KEf™ Deliverables (including the confidentiality level and Delivery Schedule for each MIPS Deliverable):
Release Control Number 24KEf031720090202-2.5.1
The MIPS32® 24KEf™ Deliverables are provided electronically as a bundle.
| Deliverable | Document or Part Number |
Restricted Confidential |
Internal Confidential |
External Confidential |
Commercial | Delivery Date* | ||||||
| Documentation | ||||||||||||
| Release Notes: Release Change Summary |
MD00489 | Ö | Within 2 weeks of signing agreement | |||||||||
| Known Issues: Non-RTL Issues and Workarounds |
MD00490 | Ö | Within 2 weeks of signing agreement | |||||||||
| MIPS32 24K and 24KE Processor Core Family Implementer’s Guide |
MD00347 | Ö | Within 2 weeks of signing agreement | |||||||||
| MIPS32 24K and 24KE Processor Core Family Integrator’s Guide |
MD00344 | Ö | Within 2 weeks of signing agreement | |||||||||
| MIPS32 24KE Processor Core Family Software User’s Manual |
MD00468 | Ö | Within 2 weeks of signing agreement | |||||||||
|
Programming the MIPS32 24KE Core Family |
MD00458 | Ö | Within 2 weeks of signing agreement | |||||||||
| MIPS32 24KE Processor Core Family RTL Errata Sheet |
MD00469 | Ö | Within 2 weeks of signing agreement | |||||||||
| MIPS32 24KEf Processor Core Datasheet |
MD00446 | Ö | Within 2 weeks of signing agreement | |||||||||
| Cache SRAM Excerpt from Implementor’s Guide for MIPS32 24K, 24KE, and 34K Cores |
MD00400 | Ö | Within 2 weeks of signing agreement | |||||||||
|
MIPS® Physical Design Guide |
MD00606 | Ö | Within 2 weeks of signing agreement | |||||||||
| OCP2.2 Compliance Checker for MIPS32® Cores |
MD00596 | Ö | Within 2 weeks of signing agreement | |||||||||
|
MIPS32® 24KE™ Processor Core System Users Manual |
MD00650 | Ö | Within 2 weeks of signing agreement | |||||||||
|
Coprocessor 2 Module Template Application Note for MIPS32 24K and 24KE Cores |
MD00425 | Ö | Within 2 weeks of signing agreement | |||||||||
| Cache Configuration Application Note |
MD00213 | Ö | Within 2 weeks of signing agreement | |||||||||
|
Converting ELF Files for Verilog Simulation - ELFVIEW Application Note |
MD00338 | Ö | Within 2 weeks of signing agreement | |||||||||
| EJTAG Specification |
MD00047 | Ö | Within 2 weeks of signing agreement | |||||||||
28
MIPS Confidential
Certain confidential information contained in this document, marked by brackets, has been omitted and filed separately with the Securities and Exchange Commission pursuant to Rule 24b-2 of the Securities Exchange Act of 1934, as amended.
| Deliverable | Document or Part Number |
Restricted Confidential |
Internal Confidential |
External Confidential |
Commercial | Delivery Date* | ||||||
| EJTAG Implementation Application Note |
MD00071 | Ö | Within 2 weeks of signing agreement | |||||||||
| The PDtrace Interface and Trace Control Block Specification |
MD00439 | Ö | Within 2 weeks of signing agreement | |||||||||
| Using PDtrace with SDE and System Navigator for MIPS Cores |
MD00543 | Ö | Within 2 weeks of signing agreement | |||||||||
| Core Coprocessor Interface Specification |
MD00068 | Ö | Within 2 weeks of signing agreement | |||||||||
| MIPS32 Architecture For Programmers Volume I: Introduction to the MIPS32® Architecture |
MD00082 | Ö | Within 2 weeks of signing agreement | |||||||||
| MIPS32 Architecture For Programmers Volume II: The MIPS32 Instruction Set |
MD00086 | Ö | Within 2 weeks of signing agreement | |||||||||
| MIPS32 Architecture For Programmers Volume III: The MIPS32 Privileged Resource Architecture |
MD00090 | Ö | Within 2 weeks of signing agreement | |||||||||
| MIPS32 Architecture For Programmers Volume IV-a: The MIPS16e Application-Specific Extension to the MIPS32 Architecture |
MD00076 | Ö | Within 2 weeks of signing agreement | |||||||||
| MIPS32 Architecture For Programmers Volume IV-e: The MIPS DSP Application-Specific Extension to the MIPS32 Architecture |
MD00374 | Ö | Within 2 weeks of signing agreement | |||||||||
| MINI Testbench Specification |
MD00493 | Ö | Within 2 weeks of signing agreement | |||||||||
|
Effective Programming of the 24KE and the 34K Core Families for DSP Code |
MD00475 | Ö | Within 2 weeks of signing agreement | |||||||||
| JPEG Decoder Optimization for the 24KE™ and the 34K™ Core Families |
MD00483 | Ö | Within 2 weeks of signing agreement | |||||||||
|
Optimizing the ITU-T G.729AB Codec for the MIPS32® 24KE™ and 34K™ Core Families |
MD00484 | Ö | Within 2 weeks of signing agreement | |||||||||
|
Efficient DSP ASE Programming in C: Tips and Tricks |
MD00485 | Ö | Within 2 weeks of signing agreement | |||||||||
| MP3 Decoder Optimization for the 24KE™ and the 34K™ Core Families |
MD00495 | Ö | Within 2 weeks of signing agreement | |||||||||
| H.263 Decoder Optimization for the 24KE™ and the 34K™ Core Families |
MD00533 | Ö | Within 2 weeks of signing agreement | |||||||||
|
Optimizing G.722.2 Speech Codec for the MIPS32® 24KE™ and 34K™ Cores |
MD00551 | Ö | Within 2 weeks of signing agreement |
29
MIPS Confidential
Certain confidential information contained in this document, marked by brackets, has been omitted and filed separately with the Securities and Exchange Commission pursuant to Rule 24b-2 of the Securities Exchange Act of 1934, as amended.
| Deliverable |
Document or Part Number |
Restricted Confidential |
Internal Confidential |
External Confidential |
Commercial | Delivery Date* | ||||||
| Working with ScratchPad RAMs for MIPS32® 24K® and 34K™ Cores Application Note |
MD00540 | Ö | Within 2 weeks of signing agreement | |||||||||
| Design Data | ||||||||||||
| Verilog RTL for MIPS32 24KEf Core |
Ö | Within 2 weeks of signing agreement | ||||||||||
| Configuration Tools | ||||||||||||
|
Configuration GUI tool |
Ö | Within 2 weeks of signing agreement | ||||||||||
| Synthesis Support | ||||||||||||
| Reference flow scripts for Synopsys tools |
Ö1 | Within 2 weeks of signing agreement | ||||||||||
| Reference flow scripts for Cadence tools |
Ö1 | Within 2 weeks of signing agreement | ||||||||||
| Reference flow scripts for Magma tools |
Ö1 | Within 2 weeks of signing agreement | ||||||||||
| Synplicity Synplify Pro – FPGA synthesis scripts |
Ö1 | Within 2 weeks of signing agreement | ||||||||||
| Simulation Models | ||||||||||||
| MIPS32 24KE cycle-exact simulation model (VMC) |
Ö2,3,4 | Within 2 weeks of signing agreement | ||||||||||
| Simulation Support | ||||||||||||
| Build and run scripts |
Ö1 | Within 2 weeks of signing agreement | ||||||||||
| Simulation and verification test bench RTL |
Ö | Within 2 weeks of signing agreement | ||||||||||
| Verification Suite | ||||||||||||
| Memory image for Core diagnostics |
Ö | Within 2 weeks of signing agreement | ||||||||||
| DFT Support - Tools | ||||||||||||
| Mentor – DFTAdvisor and FastScan scripts |
Ö1 | Within 2 weeks of signing agreement | ||||||||||
| Synopsys – DFT Compiler and TetraMAX scripts |
Ö1 | Within 2 weeks of signing agreement | ||||||||||
30
MIPS Confidential
Certain confidential information contained in this document, marked by brackets, has been omitted and filed separately with the Securities and Exchange Commission pursuant to Rule 24b-2 of the Securities Exchange Act of 1934, as amended.
| Deliverable |
Document or Part Number |
Restricted Confidential |
Internal Confidential |
External Confidential |
Commercial | Delivery Date* | ||||||
| Timing Analysis | ||||||||||||
| Reference STA scripts for Synopsys PrimeTime tools |
Ö1 | Within 2 weeks of signing agreement | ||||||||||
| Power Analysis | ||||||||||||
| Synopsys PrimePower scripts |
Ö1 | Within 2 weeks of signing agreement | ||||||||||
| 1 | Licensee may modify as necessary to support chip development. |
| 2 | Licensee’s customer may not modify or distribute. |
| 3 | The VMC model is supported on Sun-Solaris and x86 RedHat Linux only. |
| 4 | The VMC model is managed with FLEXlm license keys and Licensee shall be provided upon request with up to 40 keys. Additional keys for the VMC model are available upon request at the then-current license fees. |
| * | Delivery Date is subject to the conditions set forth in Section 2 of this Technology Schedule. |
The MIPSsim Deliverables are provided electronically as a bundle:
| Deliverable |
Document or Part Number |
Restricted Confidential |
Internal Confidential |
External Confidential |
Commercial | Delivery Date* | ||||||
| Instruction Set Simulator | ||||||||||||
| MIPS32 Instruction Set Simulator for 24KE Processor Core Family for RedHat Linux |
PN00206 | Ö1 | Within 2 weeks of signing agreement | |||||||||
| MIPS32 Instruction Set Simulator for 24KE Processor Core Family for Microsoft Windows |
PN00205 | Ö1 | Within 2 weeks of signing agreement | |||||||||
| Documentation | ||||||||||||
| MIPSsim Software Release Notes for 24KE Cores |
MD00457 | Ö | Within 2 weeks of signing agreement | |||||||||
| MIPSsim Software Getting Started Guide for 24KE Cores |
MD00456 | Ö2 | Within 2 weeks of signing agreement | |||||||||
| MIPSsim Software Integrator’s Guide |
MD00357 | Ö2 | Within 2 weeks of signing agreement | |||||||||
| Microprocessor Debug Interface (MDI) Specification |
MD00412 | Ö | Within 2 weeks of signing agreement | |||||||||
| 1 | The MIPSsim Deliverables are managed with FLEXlm license keys and Licensee shall be provided upon request with up to 10 keys. Additional keys for MIPSsim are available upon request at the then-current license fees. |
| 2 | Licensee’s customer may not modify or distribute. |
| * | Delivery Date is subject to the conditions set forth in Section 2 of this Technology Schedule. |
31
MIPS Confidential
Certain confidential information contained in this document, marked by brackets, has been omitted and filed separately with the Securities and Exchange Commission pursuant to Rule 24b-2 of the Securities Exchange Act of 1934, as amended.
The MIPS BFM Deliverables are provided electronically as a bundle:
| Deliverable |
Document or Part Number |
Restricted Confidential |
Internal Confidential |
External Confidential |
Commercial | Delivery Date* | ||||||
| Bus Functional Model | ||||||||||||
| Bus Functional Model for the MIPS32 24KE Processor Core Family for RedHat Linux |
PN00100 | Ö1 | Within 2 weeks of signing agreement | |||||||||
| Bus Functional Model for the MIPS32 24KE Processor Core Family for Microsoft Windows |
PN00099 | Ö1 | Within 2 weeks of signing agreement | |||||||||
| Documentation | ||||||||||||
| MIPS32 24KE Bus Functional Model Release Notes |
MD00461 | Ö | Within 2 weeks of signing agreement | |||||||||
| MIPS32 24KE Bus Functional Model Software User’s Manual |
MD00459 | Ö2 | Within 2 weeks of signing agreement | |||||||||
| MIPS32 24KE Bus Functional Model Integrator’s Guide |
MD00460 | Ö2 | Within 2 weeks of signing agreement | |||||||||
| Debugging an Integrated MIPSsim and MIPS BFM |
MD00381 | Ö2 | Within 2 weeks of signing agreement | |||||||||
| 1 | The MIPS BFM Deliverables are managed with FLEXlm license keys and Licensee shall be provided upon request with up to 10 keys. Additional keys for the BFM are available upon request at the then-current license fees. |
| 2 | Licensee’s customer may not modify or distribute. |
| * | Delivery Date is subject to the conditions set forth in Section 2 of this Technology Schedule. |
32
MIPS Confidential
Certain confidential information contained in this document, marked by brackets, has been omitted and filed separately with the Securities and Exchange Commission pursuant to Rule 24b-2 of the Securities Exchange Act of 1934, as amended.
1. Licensed MIPS Core: MIPS32® 34Kc™ Synthesizable Processor Core
2. MIPS32® 34Kc™ Deliverables (including the confidentiality level and Delivery Schedule for each MIPS Deliverable):
Release Control Number: 34Kc03172009202-2.5.1
The MIPS32® 34Kc™ Deliverables are provided electronically as a bundle.
| Deliverable |
Document or Part Number |
Restricted Confidential |
Internal Confidential |
External Confidential |
Commercial | Delivery Date* | ||||||
| Documentation | ||||||||||||
| MIPS32® 34K™ Processor Core Family Implementor’s Guide |
MD00414 | Ö | Within 2 weeks of signing agreement | |||||||||
| MIPS32® 34K™ Processor Core Family Integrator’s Guide |
MD00415 | Ö | Within 2 weeks of signing agreement | |||||||||
| MIPS32® 34K™ Processor Core Family Software User’s Manual |
MD00534 | Ö | Within 2 weeks of signing agreement | |||||||||
| MIPS32® 34K™ Processor Core System User’s Manual |
MD00651 | Ö | Within 2 weeks of signing agreement | |||||||||
| Programming the MIPS32® 34K™ Processor Core Family |
MD00427 | Ö | Within 2 weeks of signing agreement | |||||||||
| MIPS® MT Principles of Operation |
MD00452 | Ö | Within 2 weeks of signing agreement | |||||||||
| Effective Programming of the 24KE and the 34K Core Families for DSP Code |
MD00475 | Ö | Within 2 weeks of signing agreement | |||||||||
| MIPS32® 34K™ Processor Core Family RTL Errata Sheet |
MD00417 | Ö | Within 2 weeks of signing agreement | |||||||||
| MIPS32® 34Kc™ Processor Core Datasheet |
MD00418 | Ö | Within 2 weeks of signing agreement | |||||||||
| MIPS® Physical Design Guide |
MD00606 | Ö | Within 2 weeks of signing agreement | |||||||||
| EJTAG Specification |
MD00047 | Ö | Within 2 weeks of signing agreement | |||||||||
| EJTAG Implementation Application Note |
MD00071 | Ö | Within 2 weeks of signing agreement | |||||||||
| Core Coprocessor Interface Specification |
MD00068 | Ö | Within 2 weeks of signing agreement | |||||||||
| MIPS32® Architecture For Programmers Volume I: Introduction to the MIPS32® Architecture |
MD00082 | Ö | Within 2 weeks of signing agreement | |||||||||
| MIPS32® Architecture For Programmers Volume II: The MIPS32® Instruction Set |
MD00086 | Ö | Within 2 weeks of signing agreement | |||||||||
33
MIPS Confidential
Certain confidential information contained in this document, marked by brackets, has been omitted and filed separately with the Securities and Exchange Commission pursuant to Rule 24b-2 of the Securities Exchange Act of 1934, as amended.
| Deliverable |
Document or Part Number |
Restricted Confidential |
Internal Confidential |
External Confidential |
Commercial | Delivery Date* | ||||||
| MIPS32® Architecture For Programmers Volume III: The MIPS32® Privileged Resource Architecture |
MD00090 | Ö | Within 2 weeks of signing agreement | |||||||||
| MIPS32® Architecture For Programmers Volume IV-a: The MIPS16e™ Application-Specific Extension to the MIPS32® Architecture |
MD00076 | Ö | Within 2 weeks of signing agreement | |||||||||
| MIPS32® Architecture For Programmers Volume IV-e: The MIPS DSP Application-Specific Extension to the MIPS32® Architecture |
MD00374 | Ö | Within 2 weeks of signing agreement | |||||||||
| MIPS32® Architecture For Programmers Volume IV-f: The MIPS MT Application-Specific Extension to the MIPS32® Architecture |
MD00378 | Ö | Within 2 weeks of signing agreement | |||||||||
| The PDtrace™ Interface and Trace Control Block Specification |
MD00439 | Ö | Within 2 weeks of signing agreement | |||||||||
| OCP2.2 Compliance Checker for MIPS32® Cores |
MD00596 | Ö | Within 2 weeks of signing agreement | |||||||||
| Using PDtrace with SDE and System Navigator for MIPS Cores |
MD00543 | Ö | Within 2 weeks of signing agreement | |||||||||
| Cache Configuration Application Note |
MD00213 | Ö | Within 2 weeks of signing agreement | |||||||||
| Converting ELF Files for Verilog Simulation - ELFVIEW Application Note |
MD00338 | Ö | Within 2 weeks of signing agreement | |||||||||
| Cache SRAM Excerpt from Implementor’s Guide for MIPS32® 24K®, 24KE™, and 34K™ Cores |
MD00400 | Ö | Within 2 weeks of signing agreement | |||||||||
| Working with ScratchPad RAMs for MIPS32® 24K® and 34K™ Cores Application Note |
MD00540 | Ö | Within 2 weeks of signing agreement | |||||||||
| Coprocessor 2 Module Template Application Note for MIPS32® 24K®, 24KE™, and 34K™ Cores |
MD00425 | Ö | Within 2 weeks of signing agreement | |||||||||
| 34K™ Core Release Notes |
MD00491 | Ö | Within 2 weeks of signing agreement |
34
MIPS Confidential
Certain confidential information contained in this document, marked by brackets, has been omitted and filed separately with the Securities and Exchange Commission pursuant to Rule 24b-2 of the Securities Exchange Act of 1934, as amended.
| Deliverable |
Document or Part Number |
Restricted Confidential |
Internal Confidential |
External Confidential |
Commercial | Delivery Date* | ||||||
| 34K™ Core Known Issues |
MD00492 | Ö | Within 2 weeks of signing agreement | |||||||||
| MINI Testbench Specification |
MD00493 | Ö | Within 2 weeks of signing agreement | |||||||||
| MP3 Decoder Optimization for the 24KE™ and the 34K™ Core Families |
MD00495 | Ö | Within 2 weeks of signing agreement | |||||||||
| H.263 Decoder Optimization for the 24KE™ and the 34K™ Core Families |
MD00533 | Ö | Within 2 weeks of signing agreement | |||||||||
| Increasing Application Throughput on the MIPS32® 34K™ Core Family with Multithreading |
MD00535 | Ö | Within 2 weeks of signing agreement | |||||||||
|
Multi-Threading for Efficient Set Top Box SoC Architectures |
MD00545 | Ö | Within 2 weeks of signing agreement | |||||||||
|
Multi-Threading Applications on the MIPS32® 34K™ Core |
MD00547 | Ö | Within 2 weeks of signing agreement | |||||||||
| Using the MIPS32® 34K™ Core Performance Counters |
MD00548 | Ö | Within 2 weeks of signing agreement | |||||||||
| Optimizing G.722.2 Speech Codec for the MIPS32® 24KE™ and 34K™ Cores |
MD00551 | Ö | Within 2 weeks of signing agreement | |||||||||
| JPEG Decoder Optimization for the 24KE™ and the 34K™ Core Families |
MD00483 | Ö | Within 2 weeks of signing agreement | |||||||||
| Optimizing the ITU-T G.729AB Codec for the MIPS32® 24KE™ and 34K™ Core Families |
MD00484 | Ö | Within 2 weeks of signing agreement | |||||||||
| Efficient DSP ASE Programming in C: Tips and Tricks |
MD00485 | Ö | Within 2 weeks of signing agreement | |||||||||
| Design Data | ||||||||||||
| Verilog RTL for MIPS32® 34Kc™ Core |
Ö | Within 2 weeks of signing agreement | ||||||||||
| Configuration Tools | ||||||||||||
|
Configuration GUI tool |
Ö | Within 2 weeks of signing agreement | ||||||||||
| Synthesis Support | ||||||||||||
| Reference flow scripts for Synopsys tools |
Ö1 | Within 2 weeks of signing agreement | ||||||||||
| Reference flow scripts for Cadence tools |
Ö1 | Within 2 weeks of signing agreement | ||||||||||
| Reference flow scripts for Magma tools |
Ö1 | Within 2 weeks of signing agreement | ||||||||||
35
MIPS Confidential
Certain confidential information contained in this document, marked by brackets, has been omitted and filed separately with the Securities and Exchange Commission pursuant to Rule 24b-2 of the Securities Exchange Act of 1934, as amended.
| Deliverable |
Document or Part Number |
Restricted Confidential |
Internal Confidential |
External Confidential |
Commercial | Delivery Date* | ||||||
| Synplicity Synplify Pro – FPGA synthesis scripts |
Ö1 | Within 2 weeks of signing agreement | ||||||||||
| Simulation Models | ||||||||||||
| MIPS32® 34K™ cycle-exact simulation model (VMC) |
Ö2,3,4 | Within 2 weeks of signing agreement | ||||||||||
| Simulation Support | ||||||||||||
| Build and run scripts |
Ö1 | Within 2 weeks of signing agreement | ||||||||||
| Simulation and verification test bench RTL |
Ö | Within 2 weeks of signing agreement | ||||||||||
| Verification Suite | ||||||||||||
| Memory image for Core diagnostics |
Ö | Within 2 weeks of signing agreement | ||||||||||
| DFT Support – Tools | ||||||||||||
| Mentor – DFTAdvisor and FastScan scripts |
Ö1 | Within 2 weeks of signing agreement | ||||||||||
| Synopsys – DFT Compiler and TetraMAX scripts |
Ö1 | Within 2 weeks of signing agreement | ||||||||||
| Timing Analysis | ||||||||||||
| Reference STA scripts for Synopsys PrimeTime tools |
Ö1 | Within 2 weeks of signing agreement | ||||||||||
| Power Analysis | ||||||||||||
| Synopsys PrimePower scripts |
Ö1 | Within 2 weeks of signing agreement | ||||||||||
| 1 | Licensee may modify as necessary to support chip development. |
| 2 | Licensee’s customer may not modify or distribute. |
| 3 | The VMC model is supported on Sun-Solaris and x86 RedHat Linux only. |
| 4 | The VMC model is managed with FLEXlm license keys and Licensee shall be provided upon request with up to 40 keys. Additional keys for the VMC model are available upon request at the then-current license fees. |
| * | Delivery Date is subject to the conditions set forth in Section 2 of this Technology Schedule. |
36
MIPS Confidential
Certain confidential information contained in this document, marked by brackets, has been omitted and filed separately with the Securities and Exchange Commission pursuant to Rule 24b-2 of the Securities Exchange Act of 1934, as amended.
The MIPSsim Deliverables are provided electronically as a bundle:
| Deliverable |
Document or Part Number |
Restricted Confidential |
Internal Confidential |
External Confidential |
Commercial | Delivery Date* | ||||||
| Instruction Set Simulator | ||||||||||||
| MIPS32® Instruction Set Simulator for the 34K™ Processor Core Family for RedHat Linux |
PN00151 | Ö1 | Within 2 weeks of signing agreement | |||||||||
| MIPS32® Instruction Set Simulator for the 34K™ Processor Core Family for Microsoft Windows |
PN00152 | Ö1 | Within 2 weeks of signing agreement | |||||||||
| Documentation | ||||||||||||
| MIPSsim™ 34K™ Release Notes |
MD00420 | Ö | Within 2 weeks of signing agreement | |||||||||
| MIPSsim™ Getting Started for MIPS32® 34K™ Cores |
MD00421 | Ö2 | Within 2 weeks of signing agreement | |||||||||
| MIPSsim™ Software Integrator’s Guide |
MD00357 | Ö2 | Within 2 weeks of signing agreement | |||||||||
| Microprocessor Debug Interface (MDI) Specification |
MD00412 | Ö | Within 2 weeks of signing agreement | |||||||||
| 1 | The MIPSsim Deliverables are managed with FLEXlm license keys and Licensee shall be provided upon request with up to 10 keys. Additional keys for MIPSsim are available upon request at the then-current license fees. |
| 2 | Licensee’s customer may not modify or distribute. |
| * | Delivery Date is subject to the conditions set forth in Section 2 of this Technology Schedule. |
37
MIPS Confidential
Certain confidential information contained in this document, marked by brackets, has been omitted and filed separately with the Securities and Exchange Commission pursuant to Rule 24b-2 of the Securities Exchange Act of 1934, as amended.
The MIPS BFM Deliverables are provided electronically as a bundle:
| Deliverable |
Document or Part Number |
Restricted Confidential |
Internal Confidential |
External Confidential |
Commercial | Delivery Date* | ||||||
| Bus Functional Model | ||||||||||||
| Bus Functional Model for the MIPS32® 34K™ Processor Core Family for RedHat Linux |
PN00154 | Ö1 | Within 2 weeks of signing agreement | |||||||||
| Bus Functional Model for the MIPS32® 34K™ Processor Core Family for Microsoft Windows |
PN00155 | Ö1 | Within 2 weeks of signing agreement | |||||||||
| Documentation | ||||||||||||
| MIPS32® 34K™ Bus Functional Model Release Notes |
MD00422 | Ö | Within 2 weeks of signing agreement | |||||||||
| MIPS32® 34K™ Bus Functional Model Software User’s Manual |
MD00423 | Ö2 | Within 2 weeks of signing agreement | |||||||||
| MIPS32® 34K™ Bus Functional Model Integrator’s Guide |
MD00424 | Ö2 | Within 2 weeks of signing agreement | |||||||||
| Debugging an Integrated MIPSsim™ and MIPS BFM |
MD00381 | Ö2 | Within 2 weeks of signing agreement | |||||||||
| 1 | The MIPS BFM Deliverables are managed with FLEXlm license keys and Licensee shall be provided upon request with up to 10 keys. Additional keys for the BFM are available upon request at the then-current license fees. |
| 2 | Licensee’s customer may not modify or distribute. |
| * | Delivery Date is subject to the conditions set forth in Section 2 of this Technology Schedule. |
38
MIPS Confidential
Certain confidential information contained in this document, marked by brackets, has been omitted and filed separately with the Securities and Exchange Commission pursuant to Rule 24b-2 of the Securities Exchange Act of 1934, as amended.
1. Licensed MIPS Core: MIPS32® 34Kf™ Synthesizable Processor Core
2. MIPS32® 34Kf™ Deliverables (including the confidentiality level and Delivery Schedule for each MIPS Deliverable):
Release Control Number: 34Kf031720090202-2.5.1
The MIPS32® 34Kf™ Deliverables are provided electronically as a bundle.
| Deliverable |
Document or Part Number |
Restricted Confidential |
Internal Confidential |
External Confidential |
Commercial | Delivery Date* | ||||||
| Documentation | ||||||||||||
| MIPS32® 34K™ Processor Core Family Implementor’s Guide |
MD00414 | Ö | Within 2 weeks of signing agreement | |||||||||
| MIPS32® 34K™ Processor Core Family Integrator’s Guide |
MD00415 | Ö | Within 2 weeks of signing agreement | |||||||||
| MIPS32® 34K™ Processor Core Family Software User’s Manual |
MD00534 | Ö | Within 2 weeks of signing agreement | |||||||||
| Programming the MIPS32® 34K™ Processor Core Family |
MD00427 | Ö | Within 2 weeks of signing agreement | |||||||||
| MIPS® MT Principles of Operation |
MD00452 | Ö | Within 2 weeks of signing agreement | |||||||||
| Effective Programming of the 24KE and the 34K Core Families for DSP Code |
MD00475 | Ö | Within 2 weeks of signing agreement | |||||||||
| MIPS32® 34K™ Processor Core Family RTL Errata Sheet |
MD00417 | Ö | Within 2 weeks of signing agreement | |||||||||
| MIPS32® 34Kf™ Processor Core Datasheet |
MD00419 | Ö | Within 2 weeks of signing agreement | |||||||||
| MIPS® Physical Design Guide |
MD00606 | Ö | Within 2 weeks of signing agreement | |||||||||
| OCP2.2 Compliance Checker for MIPS32® Cores |
MD00596 | Ö | Within 2 weeks of signing agreement | |||||||||
| MIPS32® 34K™ Processor Core System Users Manual |
MD00651 | Ö | Within 2 weeks of signing agreement | |||||||||
| EJTAG Specification |
MD00047 | Ö | Within 2 weeks of signing agreement | |||||||||
| EJTAG Implementation Application Note |
MD00071 | Ö | Within 2 weeks of signing agreement | |||||||||
| Core Coprocessor Interface Specification |
MD00068 | Ö | Within 2 weeks of signing agreement | |||||||||
| MIPS32® Architecture For Programmers Volume I: Introduction to the MIPS32® Architecture |
MD00082 | Ö | Within 2 weeks of signing agreement | |||||||||
| MIPS32® Architecture For Programmers Volume II: The MIPS32® Instruction Set |
MD00086 | Ö | Within 2 weeks of signing agreement | |||||||||
39
MIPS Confidential
Certain confidential information contained in this document, marked by brackets, has been omitted and filed separately with the Securities and Exchange Commission pursuant to Rule 24b-2 of the Securities Exchange Act of 1934, as amended.
| Deliverable |
Document or Part Number |
Restricted Confidential |
Internal Confidential |
External Confidential |
Commercial | Delivery Date* | ||||||
| MIPS32® Architecture For Programmers Volume III: The MIPS32® Privileged Resource Architecture |
MD00090 | Ö | Within 2 weeks of signing agreement | |||||||||
| MIPS32® Architecture For Programmers Volume IV-a: The MIPS16e™ Application-Specific Extension to the MIPS32® Architecture |
MD00076 | Ö | Within 2 weeks of signing agreement | |||||||||
| MIPS32® Architecture For Programmers Volume IV-e: The MIPS DSP Application-Specific Extension to the MIPS32® Architecture |
MD00374 | Ö | Within 2 weeks of signing agreement | |||||||||
| MIPS32® Architecture For Programmers Volume IV-f: The MIPS MT Application-Specific Extension to the MIPS32® Architecture |
MD00378 | Ö | Within 2 weeks of signing agreement | |||||||||
| The PDtrace™ Interface and Trace Control Block Specification |
MD00439 | Ö | Within 2 weeks of signing agreement | |||||||||
| Using PDtrace™ with SDE and System Navigator for MIPS Cores |
MD00543 | Ö | Within 2 weeks of signing agreement | |||||||||
| Cache Configuration Application Note |
MD00213 | Ö | Within 2 weeks of signing agreement | |||||||||
| Converting ELF Files for Verilog Simulation - ELFVIEW Application Note |
MD00338 | Ö | Within 2 weeks of signing agreement | |||||||||
| Cache SRAM Excerpt from Implementor’s Guide for MIPS32® 24K®, 24KE™, and 34K™ Cores |
MD00400 | Ö | Within 2 weeks of signing agreement | |||||||||
| Working with ScratchPad RAMs for MIPS32® 24K® and 34K™ Cores Application Note |
MD00540 | Ö | Within 2 weeks of signing agreement | |||||||||
| Coprocessor 2 Module Template Application Note for MIPS32® 24K®, 24KE™, and 34K™ Cores |
MD00425 | Ö | Within 2 weeks of signing agreement | |||||||||
| 34K™ Core Release Notes |
MD00491 | Ö | Within 2 weeks of signing agreement | |||||||||
| 34K™ Core Known Issues |
MD00492 | Ö | Within 2 weeks of signing agreement |
40
MIPS Confidential
Certain confidential information contained in this document, marked by brackets, has been omitted and filed separately with the Securities and Exchange Commission pursuant to Rule 24b-2 of the Securities Exchange Act of 1934, as amended.
| Deliverable |
Document or Part Number |
Restricted Confidential |
Internal Confidential |
External Confidential |
Commercial | Delivery Date* | ||||||
| MINI Testbench Specification |
MD00493 | Ö | Within 2 weeks of signing agreement | |||||||||
| MP3 Decoder Optimization for the 24KE™ and the 34K™ Core Families |
MD00495 | Ö | Within 2 weeks of signing agreement | |||||||||
| H.263 Decoder Optimization for the 24KE™ and the 34K™ Core Families |
MD00533 | Ö | Within 2 weeks of signing agreement | |||||||||
| Increasing Application Throughput on the MIPS32® 34K™ Core Family with Multithreading |
MD00535 | Ö | Within 2 weeks of signing agreement | |||||||||
|
Multi-Threading for Efficient Set Top Box SoC Architectures |
MD00545 | Ö | Within 2 weeks of signing agreement | |||||||||
|
Multi-Threading Applications on the MIPS32® 34K™ Core |
MD00547 | Ö | Within 2 weeks of signing agreement | |||||||||
| Using the MIPS32® 34K™ Core Performance Counters |
MD00548 | Ö | Within 2 weeks of signing agreement | |||||||||
| Optimizing G.722.2 Speech Codec for the MIPS32® 24KE™ and 34K™ Cores |
MD00551 | Ö | Within 2 weeks of signing agreement | |||||||||
| JPEG Decoder Optimization for the 24KE™ and the 34K™ Core Families |
MD00483 | Ö | Within 2 weeks of signing agreement | |||||||||
| Optimizing the ITU-T G.729AB Codec for the MIPS32® 24KE™ and 34K™ Core Families |
MD00484 | Ö | Within 2 weeks of signing agreement | |||||||||
| Efficient DSP ASE Programming in C: Tips and Tricks |
MD00485 | Ö | Within 2 weeks of signing agreement | |||||||||
| Design Data | ||||||||||||
| Verilog RTL for MIPS32® 34Kf™ Core |
Ö | Within 2 weeks of signing agreement | ||||||||||
| Configuration Tools | ||||||||||||
|
Configuration GUI tool |
Ö | Within 2 weeks of signing agreement | ||||||||||
| Synthesis Support | ||||||||||||
| Reference flow scripts for Synopsys tools |
Ö1 | Within 2 weeks of signing agreement | ||||||||||
| Reference flow scripts for Cadence tools |
Ö1 | Within 2 weeks of signing agreement | ||||||||||
| Reference flow scripts for Magma tools |
Ö1 | Within 2 weeks of signing agreement | ||||||||||
| Synplicity Synplify Pro – FPGA synthesis scripts |
Ö1 | Within 2 weeks of signing agreement | ||||||||||
41
MIPS Confidential
Certain confidential information contained in this document, marked by brackets, has been omitted and filed separately with the Securities and Exchange Commission pursuant to Rule 24b-2 of the Securities Exchange Act of 1934, as amended.
| Deliverable |
Document or Part Number |
Restricted Confidential |
Internal Confidential |
External Confidential |
Commercial | Delivery Date* | ||||||
| Simulation Models | ||||||||||||
| MIPS32® 34K™ cycle-exact simulation model (VMC) |
Ö2,3,4 | Within 2 weeks of signing agreement | ||||||||||
| Simulation Support | ||||||||||||
| Build and run scripts |
Ö1 | Within 2 weeks of signing agreement | ||||||||||
| Simulation and verification test bench RTL |
Ö | Within 2 weeks of signing agreement | ||||||||||
| Verification Suite | ||||||||||||
| Memory image for Core diagnostics |
Ö | Within 2 weeks of signing agreement | ||||||||||
| DFT Support – Tools | ||||||||||||
| Mentor – DFTAdvisor and FastScan scripts |
Ö1 | Within 2 weeks of signing agreement | ||||||||||
| Synopsys – DFT Compiler and TetraMAX scripts |
Ö1 | Within 2 weeks of signing agreement | ||||||||||
| Timing Analysis | ||||||||||||
| Reference STA scripts for Synopsys PrimeTime tools |
Ö1 | Within 2 weeks of signing agreement | ||||||||||
| Power Analysis | ||||||||||||
| Synopsys PrimePower scripts |
Ö1 | Within 2 weeks of signing agreement | ||||||||||
| 1 | Licensee may modify as necessary to support chip development. |
| 2 | Licensee’s customer may not modify or distribute. |
| 3 | The VMC model is supported on Sun-Solaris and x86 RedHat Linux only. |
| 4 | The VMC model is managed with FLEXlm license keys and Licensee shall be provided upon request with up to 40 keys. Additional keys for the VMC model are available upon request at the then-current license fees. |
| * | Delivery Date is subject to the conditions set forth in Section 2 of this Technology Schedule. |
42
MIPS Confidential
Certain confidential information contained in this document, marked by brackets, has been omitted and filed separately with the Securities and Exchange Commission pursuant to Rule 24b-2 of the Securities Exchange Act of 1934, as amended.
The MIPSsim Deliverables are provided electronically as a bundle:
| Deliverable |
Document or Part Number |
Restricted Confidential |
Internal Confidential |
External Confidential |
Commercial | Delivery Date* | ||||||
| Instruction Set Simulator | ||||||||||||
| MIPS32® Instruction Set Simulator for the 34K™ Processor Core Family for RedHat Linux |
PN00151 | Ö1 | Within 2 weeks of signing agreement | |||||||||
| MIPS32® Instruction Set Simulator for the 34K™ Processor Core Family for Microsoft Windows |
PN00152 | Ö1 | Within 2 weeks of signing agreement | |||||||||
| Documentation | ||||||||||||
| MIPSsim™ 34K™ Release Notes |
MD00420 | Ö | Within 2 weeks of signing agreement | |||||||||
| MIPSsim™ Getting Started for MIPS32® 34K™ Cores |
MD00421 | Ö2 | Within 2 weeks of signing agreement | |||||||||
| MIPSsim™ Software Integrator’s Guide |
MD00357 | Ö2 | Within 2 weeks of signing agreement | |||||||||
| Microprocessor Debug Interface (MDI) Specification |
MD00412 | Ö | Within 2 weeks of signing agreement | |||||||||
| 1 | The MIPSsim Deliverables are managed with FLEXlm license keys and Licensee shall be provided upon request with up to 10 keys. Additional keys for MIPSsim are available upon request at the then-current license fees. |
| 2 | Licensee’s customer may not modify or distribute. |
| * | Delivery Date is subject to the conditions set forth in Section 2 of this Technology Schedule. |
43
MIPS Confidential
Certain confidential information contained in this document, marked by brackets, has been omitted and filed separately with the Securities and Exchange Commission pursuant to Rule 24b-2 of the Securities Exchange Act of 1934, as amended.
The MIPS BFM Deliverables are provided electronically as a bundle:
| Deliverable |
Document or Part Number |
Restricted Confidential |
Internal Confidential |
External Confidential |
Commercial | Delivery Date* | ||||||
| Bus Functional Model | ||||||||||||
| Bus Functional Model for the MIPS32® 34K™ Processor Core Family for RedHat Linux |
PN00154 | Ö1 | Within 2 weeks of signing agreement | |||||||||
| Bus Functional Model for the MIPS32® 34K™ Processor Core Family for Microsoft Windows |
PN00155 | Ö1 | Within 2 weeks of signing agreement | |||||||||
| Documentation | ||||||||||||
| MIPS32® 34K™ Bus Functional Model Release Notes |
MD00422 | Ö | Within 2 weeks of signing agreement | |||||||||
| MIPS32® 34K™ Bus Functional Model Software User’s Manual |
MD00423 | Ö2 | Within 2 weeks of signing agreement | |||||||||
| MIPS32® 34K™ Bus Functional Model Integrator’s Guide |
MD00424 | Ö2 | Within 2 weeks of signing agreement | |||||||||
| Debugging an Integrated MIPSsim™ and MIPS BFM |
MD00381 | Ö2 | Within 2 weeks of signing agreement | |||||||||
| 1 | The MIPS BFM Deliverables are managed with FLEXlm license keys and Licensee shall be provided upon request with up to 10 keys. Additional keys for the BFM are available upon request at the then-current license fees. |
| 2 | Licensee’s customer may not modify or distribute. |
| * | Delivery Date is subject to the conditions set forth in Section 2 of this Technology Schedule. |
44
MIPS Confidential
Certain confidential information contained in this document, marked by brackets, has been omitted and filed separately with the Securities and Exchange Commission pursuant to Rule 24b-2 of the Securities Exchange Act of 1934, as amended.
1. Licensed MIPS Core: MIPS32® 1004Kc™ Coherent Processing System (CPS) Synthesizable Core
2. MIPS32® 1004Kc™ CPS Deliverables (including the confidentiality level and Delivery Schedule for each MIPS Deliverable):
Release Control Number: 1004Kc-2009072701-1.2.0
The MIPS32® 1004Kc™ CPS Deliverables are provided electronically as a bundle.
The confidentiality level and delivery schedule for each item is listed below.
| Deliverable |
Document or Part Number |
Restricted Confidential |
Internal Confidential |
External Confidential |
Commercial | Delivery Date* | ||||||
| Documentation | ||||||||||||
| MIPS32® 1004K™ CPS Datasheet |
MD00584 | Ö | Within 2 weeks of signing agreement | |||||||||
| MIPS32® 1004K™ CPS RTL Errata Sheet |
MD00600 | Ö | Within 2 weeks of signing agreement | |||||||||
| MIPS32® 1004K™ CPS Release Notes |
MD00598 | Ö | Within 2 weeks of signing agreement | |||||||||
| MIPS32® 1004K™ CPS Known Issues |
MD00599 | Ö | Within 2 weeks of signing agreement | |||||||||
| MIPS32® 1004K™ Processor Core Family Implementor’s Guide |
MD00621 | Ö | Within 2 weeks of signing agreement | |||||||||
| MIPS32® 1004K™ Processor Core Family Integrator’s Guide |
MD00620 | Ö | Within 2 weeks of signing agreement | |||||||||
| MIPS32® 1004K™ CPS User’s Manual |
MD00597 | Ö | Within 2 weeks of signing agreement | |||||||||
| MIPS32® 1004K™ Processor Core Family Software User’s Manual |
MD00622 | Ö | Within 2 weeks of signing agreement | |||||||||
| Programming the MIPS32® 1004K™ Coherent Processing System Family |
MD00638 | Ö | Within 2 weeks of signing agreement | |||||||||
| MIPS® Coherence Protocol Specification (AFP version) |
MD00605 | Ö | Within 2 weeks of signing agreement | |||||||||
| MIPS® MT Principles of Operation |
MD00452 | Ö | Within 2 weeks of signing agreement | |||||||||
| Effective DSP Programming Using MIPS® DSP Application Specific Extensions |
MD00475 | Ö | Within 2 weeks of signing agreement | |||||||||
| MIPS® Physical Design Guide |
MD00606 | Ö | Within 2 weeks of signing agreement | |||||||||
| EJTAG Specification |
MD00047 | Ö | Within 2 weeks of signing agreement | |||||||||
| EJTAG Implementation Application Note |
MD00071 | Ö | Within 2 weeks of signing agreement | |||||||||
45
MIPS Confidential
Certain confidential information contained in this document, marked by brackets, has been omitted and filed separately with the Securities and Exchange Commission pursuant to Rule 24b-2 of the Securities Exchange Act of 1934, as amended.
| Deliverable |
Document or Part Number |
Restricted Confidential |
Internal Confidential |
External Confidential |
Commercial | Delivery Date* | ||||||
| The PDtrace™ Interface and Trace Control Block Specification |
MD00439 | Ö | Within 2 weeks of signing agreement | |||||||||
| Core Coprocessor Interface Specification |
MD00068 | Ö | Within 2 weeks of signing agreement | |||||||||
| MIPS32® Architecture For Programmers Volume I: Introduction to the MIPS32® Architecture |
MD00082 | Ö | Within 2 weeks of signing agreement | |||||||||
| MIPS32® Architecture For Programmers Volume II: The MIPS32® Instruction Set |
MD00086 | Ö | Within 2 weeks of signing agreement | |||||||||
| MIPS32® Architecture For Programmers Volume III: The MIPS32® Privileged Resource Architecture |
MD00090 | Ö | Within 2 weeks of signing agreement | |||||||||
| MIPS32® Architecture For Programmers Volume IV-a: The MIPS16e™ Application-Specific Extension to the MIPS32® Architecture |
MD00076 | Ö | Within 2 weeks of signing agreement | |||||||||
| MIPS32® Architecture For Programmers Volume IV-e: The MIPS DSP Application-Specific Extension to the MIPS32® Architecture |
MD00374 | Ö | Within 2 weeks of signing agreement | |||||||||
| MIPS32® Architecture For Programmers Volume IV-f: The MIPS MT Application-Specific Extension to the MIPS32® Architecture |
MD00378 | Ö | Within 2 weeks of signing agreement | |||||||||
| Cache Configuration Application Note |
MD00213 | Ö | Within 2 weeks of signing agreement | |||||||||
| Converting ELF Files for Verilog Simulation - ELFVIEW Application Note |
MD00338 | Ö | Within 2 weeks of signing agreement | |||||||||
| Cache SRAM Excerpt from Implementor’s Guide for MIPS32® Cores |
MD00400 | Ö | Within 2 weeks of signing agreement | |||||||||
| Working with ScratchPad RAMs for MIPS32® Cores Application Note |
MD00540 | Ö | Within 2 weeks of signing agreement | |||||||||
| Coprocessor 2 Module Template Application Note for MIPS32® Cores |
MD00425 | Ö | Within 2 weeks of signing agreement | |||||||||
| BootCPS: Example 1004K™ Boot Code |
MD00574 | Ö | Within 2 weeks of signing agreement |
46
MIPS Confidential
Certain confidential information contained in this document, marked by brackets, has been omitted and filed separately with the Securities and Exchange Commission pursuant to Rule 24b-2 of the Securities Exchange Act of 1934, as amended.
| Deliverable |
Document or Part Number |
Restricted Confidential |
Internal Confidential |
External Confidential |
Commercial | Delivery Date* | ||||||
| MP3 Decoder Optimization using MIPS® DSP Application Specific Extensions |
MD00495 | Ö | Within 2 weeks of signing agreement | |||||||||
| H.263 Decoder Optimization using MIPS® DSP Application Specific Extensions |
MD00533 | Ö | Within 2 weeks of signing agreement | |||||||||
| Optimizing G.722.2 Speech Codec using MIPS® DSP Application Specific Extensions |
MD00551 | Ö | Within 2 weeks of signing agreement | |||||||||
| JPEG Decoder Optimization using MIPS® DSP Application Specific Extensions |
MD00483 | Ö | Within 2 weeks of signing agreement | |||||||||
| Optimizing the ITU-T G.729AB Codec using MIPS® DSP Application Specific Extensions |
MD00484 | Ö | Within 2 weeks of signing agreement | |||||||||
| Efficient DSP ASE Programming in C: Tips and Tricks |
MD00485 | Ö | Within 2 weeks of signing agreement | |||||||||
| MIPS® CorExtend® Instructions Integrator’s Guide |
MD00348 | Ö | Within 2 weeks of signing agreement | |||||||||
| Getting Started with MIPS® CorExtend® Instructions |
MD00382 | Ö | Within 2 weeks of signing agreement | |||||||||
| MIPS® Architecture Verification Programs Release Notes |
MD00120 | Ö | Within 2 weeks of signing agreement | |||||||||
| MIPS® Architecture Verification Programs User’s Manual |
MD00121 | Ö | Within 2 weeks of signing agreement | |||||||||
| MIPS® Architecture Verification Programs Errata Sheet |
MD00142 | Ö | Within 2 weeks of signing agreement | |||||||||
|
Accelerating VoIP with MIPS® CorExtend® instructions |
MD00302 | Ö | Within 2 weeks of signing agreement | |||||||||
|
Accelerating DSP Filter Loops with MIPS® CorExtend® instructions |
MD00303 | Ö | Within 2 weeks of signing agreement | |||||||||
| Mini Testbench Specification |
MD00493 | Ö | Within 2 weeks of signing agreement | |||||||||
| Design Data | ||||||||||||
| Verilog RTL for the MIPS32® 1004Kc™ CPS |
Ö | Within 2 weeks of signing agreement | ||||||||||
| Configuration Tools | ||||||||||||
|
Configuration GUI tool |
Ö | Within 2 weeks of signing agreement | ||||||||||
| Configuration GUI support for CorExtend® UDI |
Ö | Within 2 weeks of signing agreement | ||||||||||
47
MIPS Confidential
Certain confidential information contained in this document, marked by brackets, has been omitted and filed separately with the Securities and Exchange Commission pursuant to Rule 24b-2 of the Securities Exchange Act of 1934, as amended.
| Deliverable |
Document or Part Number |
Restricted Confidential |
Internal Confidential |
External Confidential |
Commercial | Delivery Date* | ||||||
| Synthesis Support | ||||||||||||
| Reference flow scripts for Synopsys tools |
Ö1 | Within 2 weeks of signing agreement | ||||||||||
| Reference flow scripts for Cadence tools |
Ö1 | Within 2 weeks of signing agreement | ||||||||||
| Reference flow scripts for Magma tools |
Ö1 | Within 2 weeks of signing agreement | ||||||||||
| Simulation Models | ||||||||||||
| MIPS32® 1004K™ CPS cycle-exact simulation model (VMC) |
Ö2,3,4 | Within 2 weeks of signing agreement | ||||||||||
| Simulation Support | ||||||||||||
| Build and run scripts |
Ö1 | Within 2 weeks of signing agreement | ||||||||||
| Simulation and verification test bench RTL |
Ö | Within 2 weeks of signing agreement | ||||||||||
| Verification Suite | ||||||||||||
| Memory image for Core diagnostics |
Ö | Within 2 weeks of signing agreement | ||||||||||
|
CorExtend® AVP scripts |
Ö | Within 2 weeks of signing agreement | ||||||||||
| DFT Support – Tools | ||||||||||||
| Mentor – DFTAdvisor and FastScan scripts |
Ö1 | Within 2 weeks of signing agreement | ||||||||||
| Synopsys – DFT Compiler and TetraMAX scripts |
Ö1 | Within 2 weeks of signing agreement | ||||||||||
| Timing Analysis | ||||||||||||
| Reference STA scripts for Synopsys PrimeTime tools |
Ö1 | Within 2 weeks of signing agreement | ||||||||||
| Power Analysis | ||||||||||||
| Synopsys PrimePower scripts |
Ö1 | Within 2 weeks of signing agreement | ||||||||||
| 1 | Licensee may modify as necessary to support chip development. |
| 2 | Licensee’s customer may not modify or distribute. |
| 3 | The VMC model is supported on Sun-Solaris and x86 RedHat Linux only. |
| 4 | The VMC model is managed with FLEXlm license keys and Licensee shall be provided upon request with up to 40 keys. Additional keys for the VMC model are available upon request at the then-current license fees. |
| * | Delivery Date is subject to the conditions set forth in Section 2 of this Technology Schedule. |
48
MIPS Confidential
Certain confidential information contained in this document, marked by brackets, has been omitted and filed separately with the Securities and Exchange Commission pursuant to Rule 24b-2 of the Securities Exchange Act of 1934, as amended.
The MIPSsim Deliverables are provided electronically as a bundle:
| Deliverable |
Document or Part Number |
Restricted Confidential |
Internal Confidential |
External Confidential |
Commercial | Delivery Date* | ||||||
| Instruction Set Simulator | ||||||||||||
| MIPS32® Instruction Set Simulator for the 1004K™ CPS Family for RedHat Linux |
PN00210 | Ö1 | Within 2 weeks of signing agreement | |||||||||
| MIPS32® Instruction Set Simulator for the 1004K™ CPS Family for Microsoft Windows |
PN00209 | Ö1 | Within 2 weeks of signing agreement | |||||||||
| Documentation | ||||||||||||
| MIPSsim™ 1004K™ CPS Release Notes |
MD00636 | Ö | Within 2 weeks of signing agreement | |||||||||
| MIPSsim™ Getting Started for MIPS32® 1004K™ CPS |
MD00637 | Ö2 | Within 2 weeks of signing agreement | |||||||||
| MIPSsim™ Software Integrator’s Guide |
MD00357 | Ö2 | Within 2 weeks of signing agreement | |||||||||
| Microprocessor Debug Interface (MDI) Specification |
MD00412 | Ö | Within 2 weeks of signing agreement | |||||||||
| 1 | The MIPSsim Deliverables are managed with FLEXlm license keys and Licensee shall be provided upon request with up to 10 keys. Additional keys for MIPSsim are available upon request at the then-current license fees. |
| 2 | Licensee’s customer may not modify or distribute. |
| * | Delivery Date is subject to the conditions set forth in Section 2 of this Technology Schedule. |
49
MIPS Confidential
Certain confidential information contained in this document, marked by brackets, has been omitted and filed separately with the Securities and Exchange Commission pursuant to Rule 24b-2 of the Securities Exchange Act of 1934, as amended.
The MIPS BFM Deliverables are provided electronically as a bundle:
| Deliverable |
Document or Part Number |
Restricted Confidential |
Internal Confidential |
External Confidential |
Commercial | Delivery Date* | ||||||
| Bus Functional Model | ||||||||||||
| Bus Functional Model for the MIPS32® 1004K™ CPS Family for RedHat Linux |
PN00213 | Ö1 | Within 2 weeks of signing agreement | |||||||||
| Bus Functional Model for the MIPS32® 1004K™ CPS Family for Microsoft Windows |
PN00212 | Ö1 | Within 2 weeks of signing agreement | |||||||||
| Documentation | ||||||||||||
| MIPS32® 1004K™ Bus Functional Model Release Notes |
MD00633 | Ö | Within 2 weeks of signing agreement | |||||||||
| MIPS32® 1004K™ Bus Functional Model Software User’s Manual |
MD00634 | Ö2 | Within 2 weeks of signing agreement | |||||||||
| Debugging with the MIPSsim™ Simulator in a Cosimulation Environment |
MD00381 | Ö2 | Within 2 weeks of signing agreement | |||||||||
| 1 | The MIPS BFM Deliverables are managed with FLEXlm license keys and Licensee shall be provided upon request with up to 10 keys. Additional keys for the BFM are available upon request at the then-current license fees. |
| 2 | Licensee’s customer may not modify or distribute. |
| * | Delivery Date is subject to the conditions set forth in Section 2 of this Technology Schedule. |
50
MIPS Confidential
Certain confidential information contained in this document, marked by brackets, has been omitted and filed separately with the Securities and Exchange Commission pursuant to Rule 24b-2 of the Securities Exchange Act of 1934, as amended.
1. Licensed MIPS Core: MIPS32® 1004Kf™ Coherent Processing System (CPS) Synthesizable Core
2. MIPS32® 1004Kf™ CPS Deliverables (including the confidentiality level and Delivery Schedule for each MIPS Deliverable):
Release Control Number: 1004Kf-2009072701-1.2.0
The MIPS32® 1004Kf™ CPS Deliverables are provided electronically as a bundle.
The confidentiality level and delivery schedule for each item is listed below.
| Deliverable |
Document or Part Number |
Restricted Confidential |
Internal Confidential |
External Confidential |
Commercial | Delivery Date* | ||||||
| Documentation | ||||||||||||
| MIPS32® 1004K™ CPS Datasheet |
MD00584 | Ö | Within 2 weeks of signing agreement | |||||||||
| MIPS32® 1004K™ CPS RTL Errata Sheet |
MD00600 | Ö | Within 2 weeks of signing agreement | |||||||||
| MIPS32® 1004K™ CPS Release Notes |
MD00598 | Ö | Within 2 weeks of signing agreement | |||||||||
| MIPS32® 1004K™ CPS Known Issues |
MD00599 | Ö | Within 2 weeks of signing agreement | |||||||||
| MIPS32® 1004K™ Processor Core Family Implementor’s Guide |
MD00621 | Ö | Within 2 weeks of signing agreement | |||||||||
| MIPS32® 1004K™ Processor Core Family Integrator’s Guide |
MD00620 | Ö | Within 2 weeks of signing agreement | |||||||||
| MIPS32® 1004K™ CPS User’s Manual |
MD00597 | Ö | Within 2 weeks of signing agreement | |||||||||
| MIPS32® 1004K™ Processor Core Family Software User’s Manual |
MD00622 | Ö | Within 2 weeks of signing agreement | |||||||||
| Programming the MIPS32® 1004K™ Coherent Processing System Family |
MD00638 | Ö | Within 2 weeks of signing agreement | |||||||||
| MIPS® Coherence Protocol Specification (AFP version) |
MD00605 | Ö | Within 2 weeks of signing agreement | |||||||||
| MIPS® MT Principles of Operation |
MD00452 | Ö | Within 2 weeks of signing agreement | |||||||||
| Effective DSP Programming Using MIPS® DSP Application Specific Extensions |
MD00475 | Ö | Within 2 weeks of signing agreement | |||||||||
| MIPS® Physical Design Guide |
MD00606 | Ö | Within 2 weeks of signing agreement | |||||||||
| EJTAG Specification |
MD00047 | Ö | Within 2 weeks of signing agreement | |||||||||
51
MIPS Confidential
Certain confidential information contained in this document, marked by brackets, has been omitted and filed separately with the Securities and Exchange Commission pursuant to Rule 24b-2 of the Securities Exchange Act of 1934, as amended.
| Deliverable |
Document or Part Number |
Restricted Confidential |
Internal Confidential |
External Confidential |
Commercial | Delivery Date* | ||||||
| EJTAG Implementation Application Note |
MD00071 | Ö | Within 2 weeks of signing agreement | |||||||||
| The PDtrace™ Interface and Trace Control Block Specification |
MD00439 | Ö | Within 2 weeks of signing agreement | |||||||||
| Core Coprocessor Interface Specification |
MD00068 | Ö | Within 2 weeks of signing agreement | |||||||||
| MIPS32® Architecture For Programmers Volume I: Introduction to the MIPS32® Architecture |
MD00082 | Ö | Within 2 weeks of signing agreement | |||||||||
| MIPS32® Architecture For Programmers Volume II: The MIPS32® Instruction Set |
MD00086 | Ö | Within 2 weeks of signing agreement | |||||||||
| MIPS32® Architecture For Programmers Volume III: The MIPS32® Privileged Resource Architecture |
MD00090 | Ö | Within 2 weeks of signing agreement | |||||||||
| MIPS32® Architecture For Programmers Volume IV-a: The MIPS16e™ Application-Specific Extension to the MIPS32® Architecture |
MD00076 | Ö | Within 2 weeks of signing agreement | |||||||||
| MIPS32® Architecture For Programmers Volume IV-e: The MIPS DSP Application-Specific Extension to the MIPS32® Architecture |
MD00374 | Ö | Within 2 weeks of signing agreement | |||||||||
| MIPS32® Architecture For Programmers Volume IV-f: The MIPS MT Application-Specific Extension to the MIPS32® Architecture |
MD00378 | Ö | Within 2 weeks of signing agreement | |||||||||
| Cache Configuration Application Note |
MD00213 | Ö | Within 2 weeks of signing agreement | |||||||||
| Converting ELF Files for Verilog Simulation - ELFVIEW Application Note |
MD00338 | Ö | Within 2 weeks of signing agreement | |||||||||
| Cache SRAM Excerpt from Implementor’s Guide for MIPS32® Cores |
MD00400 | Ö | Within 2 weeks of signing agreement | |||||||||
| Working with ScratchPad RAMs for MIPS32® Cores Application Note |
MD00540 | Ö | Within 2 weeks of signing agreement | |||||||||
| Coprocessor 2 Module Template Application Note for MIPS32® Cores |
MD00425 | Ö | Within 2 weeks of signing agreement |
52
MIPS Confidential
Certain confidential information contained in this document, marked by brackets, has been omitted and filed separately with the Securities and Exchange Commission pursuant to Rule 24b-2 of the Securities Exchange Act of 1934, as amended.
| Deliverable |
Document or Part Number |
Restricted Confidential |
Internal Confidential |
External Confidential |
Commercial | Delivery Date* | ||||||
| BootCPS: Example 1004K™ Boot Code |
MD00574 | Ö | Within 2 weeks of signing agreement | |||||||||
| MP3 Decoder Optimization using MIPS® DSP Application Specific Extensions |
MD00495 | Ö | Within 2 weeks of signing agreement | |||||||||
| H.263 Decoder Optimization using MIPS® DSP Application Specific Extensions |
MD00533 | Ö | Within 2 weeks of signing agreement | |||||||||
| Optimizing G.722.2 Speech Codec using MIPS® DSP Application Specific Extensions |
MD00551 | Ö | Within 2 weeks of signing agreement | |||||||||
| JPEG Decoder Optimization using MIPS® DSP Application Specific Extensions |
MD00483 | Ö | Within 2 weeks of signing agreement | |||||||||
| Optimizing the ITU-T G.729AB Codec using MIPS® DSP Application Specific Extensions |
MD00484 | Ö | Within 2 weeks of signing agreement | |||||||||
| Efficient DSP ASE Programming in C: Tips and Tricks |
MD00485 | Ö | Within 2 weeks of signing agreement | |||||||||
| MIPS® CorExtend® Instructions Integrator’s Guide |
MD00348 | Ö | Within 2 weeks of signing agreement | |||||||||
| Getting Started with MIPS® CorExtend® Instructions |
MD00382 | Ö | Within 2 weeks of signing agreement | |||||||||
| MIPS® Architecture Verification Programs Release Notes |
MD00120 | Ö | Within 2 weeks of signing agreement | |||||||||
| MIPS® Architecture Verification Programs User’s Manual |
MD00121 | Ö | Within 2 weeks of signing agreement | |||||||||
| MIPS® Architecture Verification Programs Errata Sheet |
MD00142 | Ö | Within 2 weeks of signing agreement | |||||||||
|
Accelerating VoIP with MIPS® CorExtend® instructions |
MD00302 | Ö | Within 2 weeks of signing agreement | |||||||||
|
Accelerating DSP Filter Loops with MIPS® CorExtend® instructions |
MD00303 | Ö | Within 2 weeks of signing agreement | |||||||||
| Mini Testbench Specification |
MD00493 | Ö | Within 2 weeks of signing agreement | |||||||||
| Design Data | ||||||||||||
| Verilog RTL for the MIPS32® 1004Kf™ CPS |
Ö | Within 2 weeks of signing agreement | ||||||||||
| Configuration Tools | ||||||||||||
| Configuration GUI tool |
Ö | Within 2 weeks of signing agreement | ||||||||||
53
MIPS Confidential
Certain confidential information contained in this document, marked by brackets, has been omitted and filed separately with the Securities and Exchange Commission pursuant to Rule 24b-2 of the Securities Exchange Act of 1934, as amended.
| Deliverable |
Document or Part Number |
Restricted Confidential |
Internal Confidential |
External Confidential |
Commercial | Delivery Date* | ||||||
|
Configuration GUI support for CorExtend® UDI |
Ö | Within 2 weeks of signing agreement | ||||||||||
| Synthesis Support | ||||||||||||
| Reference flow scripts for Synopsys tools |
Ö1 | Within 2 weeks of signing agreement | ||||||||||
| Reference flow scripts for Cadence tools |
Ö1 | Within 2 weeks of signing agreement | ||||||||||
| Reference flow scripts for Magma tools |
Ö1 | Within 2 weeks of signing agreement | ||||||||||
| Simulation Models | ||||||||||||
| MIPS32® 1004K™ CPS cycle-exact simulation model (VMC) |
Ö2,3,4 | Within 2 weeks of signing agreement | ||||||||||
| Simulation Support | ||||||||||||
| Build and run scripts |
Ö1 | Within 2 weeks of signing agreement | ||||||||||
| Simulation and verification test bench RTL |
Ö | Within 2 weeks of signing agreement | ||||||||||
| Verification Suite | ||||||||||||
| Memory image for Core diagnostics |
Ö | Within 2 weeks of signing agreement | ||||||||||
|
CorExtend® AVP scripts |
Ö | Within 2 weeks of signing agreement | ||||||||||
| DFT Support – Tools | ||||||||||||
| Mentor – DFTAdvisor and FastScan scripts |
Ö1 | Within 2 weeks of signing agreement | ||||||||||
| Synopsys – DFT Compiler and TetraMAX scripts |
Ö1 | Within 2 weeks of signing agreement | ||||||||||
| Timing Analysis | ||||||||||||
| Reference STA scripts for Synopsys PrimeTime tools |
Ö1 | Within 2 weeks of signing agreement | ||||||||||
| Power Analysis | ||||||||||||
| Synopsys PrimePower scripts |
Ö1 | Within 2 weeks of signing agreement | ||||||||||
| 1 | Licensee may modify as necessary to support chip development. |
| 2 | Licensee’s customer may not modify or distribute. |
| 3 | The VMC model is supported on Sun-Solaris and x86 RedHat Linux only. |
| 4 | The VMC model is managed with FLEXlm license keys and Licensee shall be provided upon request with up to 40 keys. Additional keys for the VMC model are available upon request at the then-current license fees. |
| * | Delivery Date is subject to the conditions set forth in Section 2 of this Technology Schedule. |
54
MIPS Confidential
Certain confidential information contained in this document, marked by brackets, has been omitted and filed separately with the Securities and Exchange Commission pursuant to Rule 24b-2 of the Securities Exchange Act of 1934, as amended.
The MIPSsim Deliverables are provided electronically as a bundle:
| Deliverable |
Document or Part Number |
Restricted Confidential |
Internal Confidential |
External Confidential |
Commercial | Delivery Date* | ||||||
| Instruction Set Simulator | ||||||||||||
| MIPS32® Instruction Set Simulator for the 1004K™ CPS Family for RedHat Linux |
PN00210 | Ö1 | Within 2 weeks of signing agreement | |||||||||
| MIPS32® Instruction Set Simulator for the 1004K™ CPS Family for Microsoft Windows |
PN00209 | Ö1 | Within 2 weeks of signing agreement | |||||||||
| Documentation | ||||||||||||
| MIPSsim™ 1004K™ CPS Release Notes |
MD00636 | Ö | Within 2 weeks of signing agreement | |||||||||
| MIPSsim™ Getting Started for MIPS32® 1004K™ CPS |
MD00637 | Ö2 | Within 2 weeks of signing agreement | |||||||||
| MIPSsim™ Software Integrator’s Guide |
MD00357 | Ö2 | Within 2 weeks of signing agreement | |||||||||
| Microprocessor Debug Interface (MDI) Specification |
MD00412 | Ö | Within 2 weeks of signing agreement | |||||||||
| 1 | The MIPSsim Deliverables are managed with FLEXlm license keys and Licensee shall be provided upon request with up to 10 keys. Additional keys for MIPSsim are available upon request at the then-current license fees. |
| 2 | Licensee’s customer may not modify or distribute. |
| * | Delivery Date is subject to the conditions set forth in Section 2 of this Technology Schedule. |
55
MIPS Confidential
Certain confidential information contained in this document, marked by brackets, has been omitted and filed separately with the Securities and Exchange Commission pursuant to Rule 24b-2 of the Securities Exchange Act of 1934, as amended.
The MIPS BFM Deliverables are provided electronically as a bundle:
| Deliverable |
Document or Part Number |
Restricted Confidential |
Internal Confidential |
External Confidential |
Commercial | Delivery Date* | ||||||
| Bus Functional Model | ||||||||||||
| Bus Functional Model for the MIPS32® 1004K™ CPS Family for RedHat Linux |
PN00213 | Ö1 | Within 2 weeks of signing agreement | |||||||||
| Bus Functional Model for the MIPS32® 1004K™ CPS Family for Microsoft Windows |
PN00212 | Ö1 | Within 2 weeks of signing agreement | |||||||||
| Documentation | ||||||||||||
| MIPS32® 1004K™ Bus Functional Model Release Notes |
MD00633 | Ö | Within 2 weeks of signing agreement | |||||||||
| MIPS32® 1004K™ Bus Functional Model Software User’s Manual |
MD00634 | Ö2 | Within 2 weeks of signing agreement | |||||||||
| Debugging with the MIPSsim™ Simulator in a Cosimulation Environment |
MD00381 | Ö2 | Within 2 weeks of signing agreement | |||||||||
| 1 | The MIPS BFM Deliverables are managed with FLEXlm license keys and Licensee shall be provided upon request with up to 10 keys. Additional keys for the BFM are available upon request at the then-current license fees. |
| 2 | Licensee’s customer may not modify or distribute. |
| * | Delivery Date is subject to the conditions set forth in Section 2 of this Technology Schedule. |
56
MIPS Confidential
Certain confidential information contained in this document, marked by brackets, has been omitted and filed separately with the Securities and Exchange Commission pursuant to Rule 24b-2 of the Securities Exchange Act of 1934, as amended.
1. Licensed MIPS Core: MIPS32® 74Kc™ Synthesizable Processor Core
2. MIPS32® 74Kc™ Core Deliverables (including the confidentiality level and Delivery Schedule for each MIPS Deliverable):
Release Control Number 74Kc-2009072702-2.3.0
The MIPS32® 74Kc™ Core Deliverables are provided electronically as a bundle.
| Deliverable | Document or
Part Number |
Restricted
Confidential |
Internal
Confidential |
External
Confidential |
Commercial | Delivery Date* | ||||||
| Documentation | ||||||||||||
| 74K™ Core Release Notes |
MD00520 | Ö | Within 2 weeks of signing agreement | |||||||||
| 74K™ Core Known Issues |
MD00273 | Ö | Within 2 weeks of signing agreement | |||||||||
|
MIPS32® 74K™ Processor Core Family Implementor’s Guide |
MD00498 | Ö | Within 2 weeks of signing agreement | |||||||||
|
MIPS32® 74K™ Processor Core Software User’s Manual |
MD00519 | Ö | Within 2 weeks of signing agreement | |||||||||
|
MIPS32® 74K™ Processor Core Family Integrator’s Guide |
MD00499 | Ö | Within 2 weeks of signing agreement | |||||||||
|
Programming the MIPS32® 74K™ Core Family |
MD00541 | Ö | Within 2 weeks of signing agreement | |||||||||
|
Programming the MIPS(R) 74K™ Core Family for DSP Applications |
MD00544 | Ö | Within 2 weeks of signing agreement | |||||||||
|
MIPS32® 74K™ Processor Core Family RTL Errata Sheet |
MD00518 | Ö | Within 2 weeks of signing agreement | |||||||||
|
MIPS32® 74Kc™ Processor Core Datasheet |
MD00496 | Ö | Within 2 weeks of signing agreement | |||||||||
|
MIPS32® 74K™ Processor Core User’s Manual |
MD00647 | Ö | Within 2 weeks of signing agreement | |||||||||
| Cache SRAM Excerpt from Implementer’s Guide for MIPS32® 74K™ Cores |
MD00521 | Ö | Within 2 weeks of signing agreement | |||||||||
|
MIPS® Physical Design Guide |
MD00606 | Ö | Within 2 weeks of signing agreement | |||||||||
| Cache Configuration Application Note |
MD00213 | Ö | Within 2 weeks of signing agreement | |||||||||
|
Converting ELF Files for Verilog Simulation - ELFVIEW Application Note |
MD00338 | Ö | Within 2 weeks of signing agreement | |||||||||
57
MIPS Confidential
Certain confidential information contained in this document, marked by brackets, has been omitted and filed separately with the Securities and Exchange Commission pursuant to Rule 24b-2 of the Securities Exchange Act of 1934, as amended.
| Deliverable | Document or
Part Number |
Restricted
Confidential |
Internal
Confidential |
External
Confidential |
Commercial | Delivery Date* | ||||||
| EJTAG Specification |
MD00047 | Ö | Within 2 weeks of signing agreement | |||||||||
| EJTAG implementation Application Note |
MD00071 | Ö | Within 2 weeks of signing agreement | |||||||||
| PDtrace™ Interface and TCB Specification |
MD00439 | Ö | Within 2 weeks of signing agreement | |||||||||
|
MIPS32® Architecture For Programmers Volume I: Introduction to the MIPS32® Architecture |
MD00082 | Ö | Within 2 weeks of signing agreement | |||||||||
|
MIPS32® Architecture For Programmers Volume II: The MIPS32® Instruction Set |
MD00086 | Ö | Within 2 weeks of signing agreement | |||||||||
|
MIPS32® Architecture For Programmers Volume III: The MIPS32® Privileged Resource Architecture |
MD00090 | Ö | Within 2 weeks of signing agreement | |||||||||
|
MIPS32® Architecture For Programmers Volume IV-a: The MIPS16e™ Application-Specific Extension to the MIPS32® Architecture |
MD00076 | Ö | Within 2 weeks of signing agreement | |||||||||
|
MIPS32® Architecture For Programmers Volume IV-e: The MIPS DSP Application-Specific Extension to the MIPS32® Architecture |
MD00374 | Ö | Within 2 weeks of signing agreement | |||||||||
| MINI Testbench Specification |
MD00493 | Ö | Within 2 weeks of signing agreement | |||||||||
| OCP Checker for MIPS32® Cores |
MD00596 | Ö | Within 2 weeks of signing agreement | |||||||||
|
CorExtend Instructions Integrator’s Guide for MIPS32® 74K™ Series Cores |
MD00523 | Ö | Within 2 weeks of signing agreement | |||||||||
| Getting Started with CorExtend Instructions for MIPS32® 74K™ Series Cores |
MD00524 | Ö | Within 2 weeks of signing agreement | |||||||||
| MIPS Architecture Verification Programs Release Notes |
MD00120 | Ö | Within 2 weeks of signing agreement | |||||||||
| MIPS Architecture Verification Programs User’s Manual |
MD00121 | Ö | Within 2 weeks of signing agreement |
58
MIPS Confidential
Certain confidential information contained in this document, marked by brackets, has been omitted and filed separately with the Securities and Exchange Commission pursuant to Rule 24b-2 of the Securities Exchange Act of 1934, as amended.
| Deliverable | Document or
Part Number |
Restricted
Confidential |
Internal
Confidential |
External
Confidential |
Commercial | Delivery Date* | ||||||
|
MIPS® Architecture Verification Programs Errata Sheet |
MD00142 | Ö | Within 2 weeks of signing agreement | |||||||||
| Design Data | ||||||||||||
| Verilog RTL for MIPS32® 74Kc™ Core |
Ö | Within 2 weeks of signing agreement | ||||||||||
| Configuration Tools | ||||||||||||
|
Configuration GUI tool |
Ö | Within 2 weeks of signing agreement | ||||||||||
|
Configuration GUI support for UDI |
Ö | Within 2 weeks of signing agreement | ||||||||||
| Synthesis Support | ||||||||||||
|
Reference flow scripts for Synopsys tools |
Ö1 | Within 2 weeks of signing agreement | ||||||||||
|
Reference flow scripts for Cadence tools |
Ö1 | Within 2 weeks of signing agreement | ||||||||||
|
Reference flow scripts for Magma tools |
Ö1 | Within 2 weeks of signing agreement | ||||||||||
|
Synplicity Synplify Pro – FPGA synthesis scripts |
Ö1 | Within 2 weeks of signing agreement | ||||||||||
| Simulation Models | ||||||||||||
|
MIPS32® 74K™ cycle-exact simulation model (VMC) |
Ö2,3,4 | Within 2 weeks of signing agreement | ||||||||||
| Simulation Support | ||||||||||||
| Build and run scripts |
Ö1 | Within 2 weeks of signing agreement | ||||||||||
|
Simulation and verification test bench RTL |
Ö | Within 2 weeks of signing agreement | ||||||||||
| Verification Suite | ||||||||||||
| Memory image for Core diagnostics |
Ö | Within 2 weeks of signing agreement | ||||||||||
|
CorExtend AVP scripts |
Ö | Within 2 weeks of signing agreement | ||||||||||
| DFT Support – Tools | ||||||||||||
| Mentor – DFTAdvisor and FastScan scripts |
Ö1 | Within 2 weeks of signing agreement | ||||||||||
| Synopsys – DFT Compiler and TetraMAX scripts |
Ö1 | Within 2 weeks of signing agreement | ||||||||||
59
MIPS Confidential
Certain confidential information contained in this document, marked by brackets, has been omitted and filed separately with the Securities and Exchange Commission pursuant to Rule 24b-2 of the Securities Exchange Act of 1934, as amended.
| Deliverable |
Document or Part Number |
Restricted Confidential |
Internal Confidential |
External Confidential |
Commercial | Delivery Date* | ||||||
| Timing Analysis | ||||||||||||
| Reference STA scripts for Synopsys PrimeTime tools |
Ö1 | Within 2 weeks of signing agreement | ||||||||||
| Power Analysis | ||||||||||||
| Synopsys PrimePower scripts |
Ö1 | Within 2 weeks of signing agreement | ||||||||||
| 1 | Licensee may modify as necessary to support chip development. |
| 2 | Licensee’s customer may not modify or distribute. |
| 3 | The VMC model is supported on x86 RedHat Linux only. |
| 4 | The VMC model is managed with FLEXlm license keys and Licensee shall be provided upon request with up to 40 keys. Additional keys for the VMC model are available upon request at the then-current license fees. |
| * | Delivery Date is subject to the conditions set forth in Section 2 of this Technology Schedule. |
The MIPSsim Deliverables are provided electronically as a bundle:
| Deliverable |
Document or Part Number |
Restricted Confidential |
Internal Confidential |
External Confidential |
Commercial | Delivery Date* | ||||||
| Instruction Set Simulator | ||||||||||||
| MIPS32® Instruction Set Simulator for the 74K™ Processor Core Family for RedHat Linux |
PN00192 | Ö1 | Within 2 weeks of signing agreement | |||||||||
| MIPS32® Instruction Set Simulator for the 74K™ Processor Core Family for Microsoft Windows |
PN00191 | Ö1 | Within 2 weeks of signing agreement | |||||||||
| Documentation | ||||||||||||
| MIPSsim™ 74K™ Release Notes |
MD00201 | Ö | Within 2 weeks of signing agreement | |||||||||
| MIPSsim™ Getting Started for MIPS32® 74K™ Cores |
MD00256 | Ö2 | Within 2 weeks of signing agreement | |||||||||
60
MIPS Confidential
Certain confidential information contained in this document, marked by brackets, has been omitted and filed separately with the Securities and Exchange Commission pursuant to Rule 24b-2 of the Securities Exchange Act of 1934, as amended.
| Deliverable |
Document or Part Number |
Restricted Confidential |
Internal Confidential |
External Confidential |
Commercial | Delivery Date* | ||||||
| MIPSsim™ Software Integrator’s Guide |
MD00357 | Ö2 | Within 2 weeks of signing agreement | |||||||||
| Microprocessor Debug Interface (MDI) Specification |
MD00412 | Ö | Within 2 weeks of signing agreement |
| 1 | The MIPSsim Deliverables are managed with FLEXlm license keys and Licensee shall be provided upon request with up to 10 keys. Additional keys for MIPSsim are available upon request at the then-current license fees. |
| 2 | Licensee’s customer may not modify or distribute. |
| * | Delivery Date is subject to the conditions set forth in Section 2 of this Technology Schedule. |
61
MIPS Confidential
Certain confidential information contained in this document, marked by brackets, has been omitted and filed separately with the Securities and Exchange Commission pursuant to Rule 24b-2 of the Securities Exchange Act of 1934, as amended.
The MIPS BFM Deliverables are provided electronically as a bundle:
| Deliverable |
Document or Part Number |
Restricted Confidential |
Internal Confidential |
External Confidential |
Commercial | Delivery Date* | ||||||
| Bus Functional Model | ||||||||||||
| Bus Functional Model for the MIPS32® 74K™ Processor Core Family for RedHat Linux |
PN00195 | Ö1 | Within 2 weeks of signing agreement | |||||||||
| Bus Functional Model for the MIPS32® 74K™ Processor Core Family for Microsoft Windows |
PN00194 | Ö1 | Within 2 weeks of signing agreement | |||||||||
| Documentation | ||||||||||||
| MIPS32® 74K™ Bus Functional Model Release Notes |
MD00272 | Ö | Within 2 weeks of signing agreement | |||||||||
| MIPS32® 74K™ Bus Functional Model Software User’s Manual |
MD00542 | Ö2 | Within 2 weeks of signing agreement | |||||||||
| MIPS32® 74K™ Bus Functional Model Integrator’s Guide |
MD00257 | Ö2 | Within 2 weeks of signing agreement | |||||||||
| Debugging an Integrated MIPSsim™ and MIPS BFM |
MD00381 | Ö2 | Within 2 weeks of signing agreement | |||||||||
| 1 | The MIPS BFM Deliverables are managed with FLEXlm license keys and Licensee shall be provided upon request with up to 10 keys. Additional keys for the BFM are available upon request at the then-current license fees. |
| 2 | Licensee’s customer may not modify or distribute. |
| * | Delivery Date is subject to the conditions set forth in Section 2 of this Technology Schedule. |
62
MIPS Confidential
Certain confidential information contained in this document, marked by brackets, has been omitted and filed separately with the Securities and Exchange Commission pursuant to Rule 24b-2 of the Securities Exchange Act of 1934, as amended.
1. Licensed MIPS Core: MIPS32® 74Kf™ Synthesizable Processor Core
2. MIPS32® 74Kf™ Core Deliverables (including the confidentiality level and Delivery Schedule for each MIPS Deliverable):
Release Control Number 74Kf-2009072702-2.3.0
The MIPS32® 74Kf™ Core Deliverables are provided electronically as a bundle.
| Deliverable |
Document or Part Number |
Restricted Confidential |
Internal Confidential |
External Confidential |
Commercial | Delivery Date* | ||||||
| Documentation | ||||||||||||
| 74K™ Core Release Notes |
MD00520 | Ö | Within 2 weeks of signing agreement | |||||||||
| 74K™ Core Known Issues |
MD00273 | Ö | Within 2 weeks of signing agreement | |||||||||
| MIPS32® 74K™ Processor Core Family Implementor’s Guide |
MD00498 | Ö | Within 2 weeks of signing agreement | |||||||||
| MIPS32® 74K™ Processor Core Software User’s Manual |
MD00519 | Ö | Within 2 weeks of signing agreement | |||||||||
| MIPS32® 74K™ Processor Core Family Integrator’s Guide |
MD00499 | Ö | Within 2 weeks of signing agreement | |||||||||
| Programming the MIPS32® 74K™ Core Family |
MD00541 | Ö | Within 2 weeks of signing agreement | |||||||||
| Programming the MIPS(R) 74K™ Core Family for DSP Applications |
MD00544 | Ö | Within 2 weeks of signing agreement | |||||||||
| MIPS32® 74K™ Processor Core Family RTL Errata Sheet |
MD00518 | Ö | Within 2 weeks of signing agreement | |||||||||
| MIPS32® 74Kf™ Processor Core Datasheet |
MD00497 | Ö | Within 2 weeks of signing agreement | |||||||||
| MIPS32® 74K™ Processor Core User’s Manual |
MD00647 | Ö | Within 2 weeks of signing agreement | |||||||||
| Cache SRAM Excerpt from Implementer’s Guide for MIPS32® 74K™ Cores |
MD00521 | Ö | Within 2 weeks of signing agreement | |||||||||
| MIPS® Physical Design Guide |
MD00606 | Ö | Within 2 weeks of signing agreement | |||||||||
| Cache Configuration Application Note |
MD00213 | Ö | Within 2 weeks of signing agreement | |||||||||
| Converting ELF Files for Verilog Simulation - ELFVIEW Application Note |
MD00338 | Ö | Within 2 weeks of signing agreement | |||||||||
63
MIPS Confidential
Certain confidential information contained in this document, marked by brackets, has been omitted and filed separately with the Securities and Exchange Commission pursuant to Rule 24b-2 of the Securities Exchange Act of 1934, as amended.
| Deliverable |
Document or Part Number |
Restricted Confidential |
Internal Confidential |
External Confidential |
Commercial | Delivery Date* | ||||||
| EJTAG Specification |
MD00047 | Ö | Within 2 weeks of signing agreement | |||||||||
| EJTAG implementation Application Note |
MD00071 | Ö | Within 2 weeks of signing agreement | |||||||||
| PDtrace™ Interface and TCB Specification |
MD00439 | Ö | Within 2 weeks of signing agreement | |||||||||
| MIPS32® Architecture For Programmers Volume I: Introduction to the MIPS32® Architecture |
MD00082 | Ö | Within 2 weeks of signing agreement | |||||||||
| MIPS32® Architecture For Programmers Volume II: The MIPS32® Instruction Set |
MD00086 | Ö | Within 2 weeks of signing agreement | |||||||||
| MIPS32® Architecture For Programmers Volume III: The MIPS32® Privileged Resource Architecture |
MD00090 | Ö | Within 2 weeks of signing agreement | |||||||||
| MIPS32® Architecture For Programmers Volume IV-a: The MIPS16e™ Application-Specific Extension to the MIPS32® Architecture |
MD00076 | Ö | Within 2 weeks of signing agreement | |||||||||
| MIPS32® Architecture For Programmers Volume IV-e: The MIPS DSP Application-Specific Extension to the MIPS32® Architecture |
MD00374 | Ö | Within 2 weeks of signing agreement | |||||||||
| MINI Testbench Specification |
MD00493 | Ö | Within 2 weeks of signing agreement | |||||||||
| OCP Checker for MIPS32® Cores |
MD00596 | Ö | Within 2 weeks of signing agreement | |||||||||
| CorExtend Instructions Integrator’s Guide for MIPS32® 74K™ Series Cores |
MD00523 | Ö | Within 2 weeks of signing agreement | |||||||||
| Getting Started with CorExtend Instructions for MIPS32® 74K™ Series Cores |
MD00524 | Ö | Within 2 weeks of signing agreement | |||||||||
| MIPS Architecture Verification Programs Release Notes |
MD00120 | Ö | Within 2 weeks of signing agreement | |||||||||
| MIPS Architecture Verification Programs User’s Manual |
MD00121 | Ö | Within 2 weeks of signing agreement |
64
MIPS Confidential
Certain confidential information contained in this document, marked by brackets, has been omitted and filed separately with the Securities and Exchange Commission pursuant to Rule 24b-2 of the Securities Exchange Act of 1934, as amended.
| Deliverable |
Document or Part Number |
Restricted Confidential |
Internal Confidential |
External Confidential |
Commercial | Delivery Date* | ||||||
| MIPS® Architecture Verification Programs Errata Sheet |
MD00142 | Ö | Within 2 weeks of signing agreement | |||||||||
| Design Data | ||||||||||||
| Verilog RTL for MIPS32® 74Kf™ Core |
Ö | Within 2 weeks of signing agreement | ||||||||||
| Configuration Tools | ||||||||||||
|
Configuration GUI tool |
Ö | Within 2 weeks of signing agreement | ||||||||||
|
Configuration GUI support for UDI |
Ö | Within 2 weeks of signing agreement | ||||||||||
| Synthesis Support | ||||||||||||
| Reference flow scripts for Synopsys tools |
Ö1 | Within 2 weeks of signing agreement | ||||||||||
| Reference flow scripts for Cadence tools |
Ö1 | Within 2 weeks of signing agreement | ||||||||||
| Reference flow scripts for Magma tools |
Ö1 | Within 2 weeks of signing agreement | ||||||||||
| Synplicity Synplify Pro – FPGA synthesis scripts |
Ö1 | Within 2 weeks of signing agreement | ||||||||||
| Simulation Models | ||||||||||||
| MIPS32® 74K™ cycle-exact simulation model (VMC) |
Ö2,3,4 | Within 2 weeks of signing agreement | ||||||||||
| Simulation Support | ||||||||||||
| Build and run scripts |
Ö1 | Within 2 weeks of signing agreement | ||||||||||
| Simulation and verification test bench RTL |
Ö | Within 2 weeks of signing agreement | ||||||||||
| Verification Suite | ||||||||||||
| Memory image for Core diagnostics |
Ö | Within 2 weeks of signing agreement | ||||||||||
| CorExtend AVP scripts |
Ö | Within 2 weeks of signing agreement | ||||||||||
| DFT Support – Tools | ||||||||||||
| Mentor – DFTAdvisor and FastScan scripts |
Ö1 | Within 2 weeks of signing agreement | ||||||||||
| Synopsys – DFT Compiler and TetraMAX scripts |
Ö1 | Within 2 weeks of signing agreement | ||||||||||
65
MIPS Confidential
Certain confidential information contained in this document, marked by brackets, has been omitted and filed separately with the Securities and Exchange Commission pursuant to Rule 24b-2 of the Securities Exchange Act of 1934, as amended.
| Deliverable |
Document or Part Number |
Restricted Confidential |
Internal Confidential |
External Confidential |
Commercial | Delivery Date* | ||||||
| Timing Analysis | ||||||||||||
| Reference STA scripts for Synopsys PrimeTime tools |
Ö1 | Within 2 weeks of signing agreement | ||||||||||
| Power Analysis | ||||||||||||
| Synopsys PrimePower scripts |
Ö1 | Within 2 weeks of signing agreement | ||||||||||
| 1 | Licensee may modify as necessary to support chip development. |
| 2 | Licensee’s customer may not modify or distribute. |
| 3 | The VMC model is supported on x86 RedHat Linux only. |
| 4 | The VMC model is managed with FLEXlm license keys and Licensee shall be provided upon request with up to 40 keys. Additional keys for the VMC model are available upon request at the then-current license fees. |
| * | Delivery Date is subject to the conditions set forth in Section 2 of this Technology Schedule. |
The MIPSsim Deliverables are provided electronically as a bundle:
| Deliverable |
Document or Part Number |
Restricted Confidential |
Internal Confidential |
External Confidential |
Commercial | Delivery Date* | ||||||
| Instruction Set Simulator | ||||||||||||
| MIPS32® Instruction Set Simulator for the 74K™ Processor Core Family for RedHat Linux |
PN00192 | Ö1 | Within 2 weeks of signing agreement | |||||||||
| MIPS32® Instruction Set Simulator for the 74K™ Processor Core Family for Microsoft Windows |
PN00191 | Ö1 | Within 2 weeks of signing agreement | |||||||||
| Documentation | ||||||||||||
| MIPSsim™ 74K™ Release Notes |
MD00201 | Ö | Within 2 weeks of signing agreement | |||||||||
| MIPSsim™ Getting Started for MIPS32® 74K™ Cores |
MD00256 | Ö2 | Within 2 weeks of signing agreement | |||||||||
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MIPS Confidential
Certain confidential information contained in this document, marked by brackets, has been omitted and filed separately with the Securities and Exchange Commission pursuant to Rule 24b-2 of the Securities Exchange Act of 1934, as amended.
| Deliverable |
Document or Part Number |
Restricted Confidential |
Internal Confidential |
External Confidential |
Commercial | Delivery Date* | ||||||
| MIPSsim™ Software Integrator’s Guide |
MD00357 | Ö2 | Within 2 weeks of signing agreement | |||||||||
| Microprocessor Debug Interface (MDI) Specification |
MD00412 | Ö | Within 2 weeks of signing agreement |
| 1 | The MIPSsim Deliverables are managed with FLEXlm license keys and Licensee shall be provided upon request with up to 10 keys. Additional keys for MIPSsim are available upon request at the then-current license fees. |
| 2 | Licensee’s customer may not modify or distribute. |
| * | Delivery Date is subject to the conditions set forth in Section 2 of this Technology Schedule. |
67
MIPS Confidential
Certain confidential information contained in this document, marked by brackets, has been omitted and filed separately with the Securities and Exchange Commission pursuant to Rule 24b-2 of the Securities Exchange Act of 1934, as amended.
The MIPS BFM Deliverables are provided electronically as a bundle:
| Deliverable |
Document or Part Number |
Restricted Confidential |
Internal Confidential |
External Confidential |
Commercial | Delivery Date* | ||||||
| Bus Functional Model | ||||||||||||
| Bus Functional Model for the MIPS32® 74K™ Processor Core Family for RedHat Linux |
PN00195 | Ö1 | Within 2 weeks of signing agreement | |||||||||
| Bus Functional Model for the MIPS32® 74K™ Processor Core Family for Microsoft Windows |
PN00194 | Ö1 | Within 2 weeks of signing agreement | |||||||||
| Documentation | ||||||||||||
| MIPS32® 74K™ Bus Functional Model Release Notes |
MD00272 | Ö | Within 2 weeks of signing agreement | |||||||||
| MIPS32® 74K™ Bus Functional Model Software User’s Manual |
MD00542 | Ö2 | Within 2 weeks of signing agreement | |||||||||
| MIPS32® 74K™ Bus Functional Model Integrator’s Guide |
MD00257 | Ö2 | Within 2 weeks of signing agreement | |||||||||
| Debugging an Integrated MIPSsim™ and MIPS BFM |
MD00381 | Ö2 | Within 2 weeks of signing agreement | |||||||||
| 1 | The MIPS BFM Deliverables are managed with FLEXlm license keys and Licensee shall be provided upon request with up to 10 keys. Additional keys for the BFM are available upon request at the then-current license fees. |
| 2 | Licensee’s customer may not modify or distribute. |
| * | Delivery Date is subject to the conditions set forth in Section 2 of this Technology Schedule. |
68
MIPS Confidential
Certain confidential information contained in this document, marked by brackets, has been omitted and filed separately with the Securities and Exchange Commission pursuant to Rule 24b-2 of the Securities Exchange Act of 1934, as amended.
1. Licensed MIPS Semiconductor IP
MIPS® SOC-it® L2 Cache Controller
2. Licensed Materials
The MIPS® SOC-it® L2 Cache Controller Licensed Materials are provided electronically as a bundle. The confidentiality level and delivery schedule for each item is listed below.
Release Control Number L20729201001-7.0
| Licensed Material | Document |
Restricted Confidential |
Internal Confidential |
External Confidential |
Commercial | Delivery Date* | ||||||
| Documentation | ||||||||||||
| MIPS® SOC-it® L2 Cache Controller Release Notes (Release Change Summary) |
MD00528 | Ö | Within 2 weeks of signing agreement | |||||||||
| MIPS® SOC-it® L2 Cache Controller Known Issues (Non-RTL Issues and Workarounds) |
MD00529 | Ö | Within 2 weeks of signing agreement | |||||||||
| MIPS SOC-it L2 Users Manual |
MD00525 | Ö | Within 2 weeks of signing agreement | |||||||||
| MIPS® SOC-it® L2 Cache Controller Errata Sheet |
MD00530 | Ö | Within 2 weeks of signing agreement | |||||||||
| MIPS® SOC-it® L2 Cache Controller Datasheet |
MD00502 | Ö | Within 2 weeks of signing agreement | |||||||||
| Design Data | ||||||||||||
| Verilog RTL for MIPS SOC-it L2 Cache Controller |
Ö | Within 2 weeks of signing agreement | ||||||||||
| Configuration Tools | ||||||||||||
|
Configuration GUI tool |
Ö | Within 2 weeks of signing agreement | ||||||||||
| Physical Design | ||||||||||||
| Reference flow scripts for Synopsys tools (ICC not included) |
Ö1 | Within 2 weeks of signing agreement | ||||||||||
| Reference flow scripts for Cadence tools |
Ö1 | Within 2 weeks of signing agreement | ||||||||||
| Reference flow scripts for Magma tools |
Ö1 | Within 2 weeks of signing agreement | ||||||||||
| Synplicity Synplify Pro – FPGA synthesis scripts |
Ö1 | Within 2 weeks of signing agreement | ||||||||||
69
MIPS Confidential
Certain confidential information contained in this document, marked by brackets, has been omitted and filed separately with the Securities and Exchange Commission pursuant to Rule 24b-2 of the Securities Exchange Act of 1934, as amended.
| Licensed Material | Document |
Restricted Confidential |
Internal Confidential |
External Confidential |
Commercial | Delivery Date* | ||||||
| Simulation Models | ||||||||||||
| MIPS MIPS SOC-it L2 cycle-exact simulation model (VMC) |
Ö2,3,4 | Within 2 weeks of signing agreement | ||||||||||
| Simulation Support | ||||||||||||
| Build and run scripts |
Ö1 | Within 2 weeks of signing agreement | ||||||||||
| DFT Support – Tools | ||||||||||||
| Mentor – DFTAdvisor and FastScan scripts |
Ö1 | Within 2 weeks of signing agreement | ||||||||||
| Synopsys – DFT Compiler and TetraMAX scripts |
Ö1 | Within 2 weeks of signing agreement | ||||||||||
| Timing Analysis | ||||||||||||
| Synopsys PrimeTime templates, pre- and post-layout |
Ö1 | Within 2 weeks of signing agreement | ||||||||||
| Power Analysis | ||||||||||||
| Synopsys PrimePower scripts |
Ö1 | Within 2 weeks of signing agreement | ||||||||||
| 1 | Licensee may modify as necessary to support chip development. |
| 2 | Licensee’s customer may not modify or distribute. |
| 3 | The VMC model is supported on Sun-Solaris and x86 RedHat Linux only. |
| 4 | The VMC model is managed with FLEXlm license keys and Licensee shall be provided upon request with up to 40 keys. Additional keys for the VMC model are available upon request at the then-current license fees. |
| * | Delivery Date is subject to the conditions set forth in Section 2 of this Technology Schedule. |
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