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UNITED STATES

SECURITIES AND EXCHANGE COMMISSION

Washington, D.C. 20549

FORM 10-K

For the year ended October 31, 2003

OR

Commission File Number 0-19807

SYNOPSYS, INC.

(Exact name of registrant as specified in its charter)

700 East Middlefield Road, Mountain View, California 94043

(Address of principal executive offices, including zip code)

(650) 584-5000

(Registrant’s telephone number, including area code)

Securities Registered Pursuant to Section 12(b) of the Act:    None

Securities Registered Pursuant to Section 12(g) of the Act:

Common Stock, $0.01 par value

(Title of Class)

Preferred Share Purchase Rights

(Title of Class)

Indicate by check mark whether the Registrant (1) has filed all reports required to be filed by Section 13 or 15(d) of the Securities Exchange Act of 1934 during the preceding 12 months (or for such shorter period that the Registrant was required to file such reports), and (2) has been subject to such filing requirements for the past 90 days.    x  Yes    ¨  No

Indicate by check mark if disclosure of delinquent filers pursuant to Item 405 of Regulation S-K is not contained herein, and will not be contained, to the best of Registrant’s knowledge, in definitive proxy or information statements incorporated by reference in Part III of this Form 10-K or any amendment to this Form 10-K.  ¨

Indicate by check mark whether the Registrant is an accelerated filer (as defined in Rule 12b-2 of the Act).     x  Yes    ¨  No

The aggregate market value of the voting and non-voting common equity held by non-affiliates computed by reference to the price at which the common equity was last sold as of the last business day of the Registrant’s most recently completed second fiscal quarter was $2,286,755,272. Excludes an aggregate of 94,085,796 shares of common stock held by officers and directors and by each person known by the Registrant to own 5% or more of the outstanding common stock on such date, giving effect to the two-for-one stock split completed on September 23, 2003. Exclusion of shares held by any of these persons should not be construed to indicate that such person possesses the power, direct or indirect, to direct or cause the direction of the management or policies of the Registrant, or that such person is controlled by or under common control with the Registrant.

On January 2, 2004, approximately 156,562,816 shares of the Registrant’s Common stock, $0.01 par value, were outstanding.

DOCUMENTS INCORPORATED BY REFERENCE

None.

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SYNOPSYS, INC.

ANNUAL REPORT ON FORM 10-K

Year ended October 31, 2003

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PART I

This Annual Report on Form 10-K, including Item 1, “Business,” includes forward-looking statements within the meaning of Section 21E of the Securities Exchange Act of 1934 that involve risks, uncertainties and assumptions. If these risks or uncertainties materialize, or if our assumptions are incorrect, our actual results could differ materially from those expressed or implied by these forward-looking statements. These statements include, but are not limited to statements concerning: our business, product and platform strategies; benefits we expect from previous and future acquisitions; completion of development of our unfinished products or further development or integration of our existing products; the shift of semiconductor manufacturing to 130 nanometer and below silicon processes; the expected customer benefits of the Milkyway^™ design database; our future research and development spending; continuation of current industry trends towards vendor consolidation; customer interest in more highly integrated tools and design flows; our expectations of the continuing success of our intellectual property and new ventures initiatives; and our expectations of our future liquidity requirements. For a discussion of certain risks or uncertainties which could cause our actual results to differ materially from those we project in these forward-looking statements, please see Part II, Item 7, “Factors That May Affect Future Results” under Management’s Discussion and Analysis of Financial Condition and Results of Operations below. The information we include in this Form 10-K is as of its filing date with the Securities and Exchange Commission and future events or circumstances could differ significantly from the forward-looking statements included in this report. We assume no obligation, and do not intend, to update these forward-looking statements.

Item 1. Business

Introduction

Synopsys, Inc. (Synopsys) is the world leader in electronic design automation (EDA) software used to design complex integrated circuits (ICs) and systems-on-chips (SoCs) in the global semiconductor and electronics industries. Our software and intellectual property products and design services provide a complete IC design and verification solution from original concept to the actual chip, enabling our customers to bring advanced products to market quickly.

We incorporated in 1986 in North Carolina and reincorporated in Delaware in 1987. Our headquarters are located at 700 East Middlefield Road, Mountain View, California 94043, telephone number (650) 584-5000. We have more than 60 offices throughout North America, Europe, Japan and Asia.

Our Annual Reports on Form 10-K, Quarterly Reports on Form 10-Q, Proxy Statements relating to our annual meetings of stockholders, Current Reports on Form 8-K and amendments to these reports are available, free of charge, on our Internet website (www.synopsys.com). We post these reports as soon as practicable after we file them with the Securities and Exchange Commission.

The Role of EDA in the Electronics Industry

Continuing technology advances in the semiconductor industry have dramatically increased the feature density, speed, power efficiency and functional capacity of semiconductors (also referred to as integrated circuits, ICs or chips).

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Combined, these advances in semiconductor technology have driven development of lower cost, higher performance computers, wireless communications networks, cell phones, hand-held personal devices, Internet routers and a wealth of other electronic devices. Each advance, however, has introduced new challenges for all participants in semiconductor production, including designers, manufacturers, equipment manufacturers and EDA software suppliers.

The IC Design Process

EDA software is central to the IC design process, as it enables designers to:

In simplified form, IC design consists of system design, logic design, functional verification, physical design and physical verification.

System Design.    In system design, the designer describes the chip’s desired functions in very basic terms using a specialized high-level computer language, typically Verilog or VHDL. This phase yields a relatively high-level, “register transfer level” (RTL) description of the chip. System design is an early stage market segment for EDA companies, as most EDA products have focused to date on logic design, functional verification and physical design and verification.

Logic Design.    Logic design, or “synthesis,” programs convert the RTL code into a logical diagram of the chip, and produce a data file known as a “net list” describing the various groups of transistors, or “gates,” to be built on the chip. Related programs insert into the design the additional circuitry that will be needed to test the chip after manufacture.

In a growing number of designs, logic synthesis is performed together with a portion of physical design. This combined process, known as “physical synthesis,” produces a data file describing the chip plus a portion of the chip’s physical layout. Also, in a growing number of SoCs, designers are increasingly performing “design planning” in which the designer determines the location of the major functional “blocks” on the SoC prior to logic synthesis.

Functional Verification.    Before and after logic design, the designer uses testbench automation and other verification tools to simulate large sets of inputs that a given IC design might confront in real-life operation. By running these extensive tests, the designer can verify that the design will function as intended.

Physical Design.    In the physical design stage, the designer plans the physical location of all of the transistors and each of the wires connecting them with a “place and route” tool. The designer first determines the location on the chip die for each block of the chip, as well as the location for each transistor within each block, a process known as “placement.” Then the designer adds the connections between the transistors, a process known as “routing.” The output of place and route programs is one or more data files that can be read by physical verification programs (as described below) or by the equipment used to manufacture the chip.

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Physical Verification.    Before sending the chip design files to a manufacturer for fabrication, the designer must perform a series of further verification steps, confirming again that the chip will still operate at the desired speed and checking to make sure that the final design complies with the specific requirements of the fabrication facility that will manufacture the chip. The designer may need to add features to the design to ensure that the chip can be manufactured successfully. The completion of this final phase is called “tapeout.”

In actual chip design, each of these steps has a number of additional elements, and designers often undertake the various design and verification steps in a different order than described above, and repeat one or more steps multiple times. Further, several of the steps, especially logic design and physical design, are becoming more integrated with each other. If at any stage of the process the designer determines the chip design will not perform as intended, the designer must go back one or more steps and correct the problem, then continue through subsequent steps. Recreating a chip’s logic design, devising and performing simulation over again, and other iterations all take time. Each such iteration adds significant costs, and makes it more difficult for the designer to meet time-to-market goals.

Current Issues Facing IC Designers

As chip technology continues to advance, our customers face three principal types of interrelated challenges:

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Synopsys Overview

We provide products and services that help our customers meet the challenges of designing leading-edge ICs. As a result of our mid-2002 acquisition of Avant! Corporation (Avant!), we now offer a comprehensive suite of system design, logic design, functional verification, physical design and physical verification products. Our March 2003 acquisition of Numerical Technologies, Inc. (Numerical) expanded our offerings of manufacturing technologies and products geared towards small geometry designs. We also sell the broadest array of pre-verified intellectual property (IP) components of any company in the EDA industry. Finally, we offer a full range of professional services, including turnkey design services, design assistance and methodology consulting.

We market our products worldwide and offer comprehensive customer service, education, consulting and support as integral components of our product offerings. We market our products primarily through our direct sales force. We have licensed our products to most of the world’s leading semiconductor, computer, communications, electronics and device companies.

Strategy

Our strategy has three principal components. First, we have historically focused, and will continue to focus, on providing our customers the most technologically advanced products to address each step in the IC design process. Second, building on the strength of our individual products, we will continue to focus on developing broad, increasingly integrated “platforms,” or collections of key individual products that are tightly integrated through the use of common technologies, to deliver enhanced value. In fiscal 2003, we created two distinct platforms: our Galaxy Design Platform and our Discovery Verification Platform. Third, we will expand our product offerings in areas offering the potential for rapid growth. For example, we have undertaken initiatives in both the intellectual property and design for manufacturing segments as described below under Products and Services.

Organization

We operate in a single segment and are currently organized into four primary groups: Implementation, Verification, Solutions and New Ventures.

Our other groups include Worldwide Sales, Worldwide Application Services, Finance, Human Resources and Facilities, and Chief Technology Office.

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Products and Services

Our products and services focus on the principal needs of semiconductor designers and, at a business level, are divided into the four groups specified above. We provide financial information regarding our products and services under Part II, Item 7, Management’s Discussion and Analysis of Financial Condition and Results of Operations—Results of Operations—Revenue—Product Groups.

Implementation Group

Galaxy Design Platform.    In February 2003, we announced the combination of many of our leading IC design products into a single, unified platform called the Galaxy^™ Design Platform. Galaxy includes the following products:

With the Galaxy Design Platform, our goal is to provide our customers a single, integrated IC design platform based on leading individual products which incorporates common libraries and consistent timing, delay calculation and constraints throughout the design process using our open Milkyway database, and yet allows designers the flexibility to integrate internally developed and third-party tools. With this advanced functionality,

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common foundation and flexibility, our Galaxy Design Platform should help reduce design times, decrease integration costs and minimize the risks inherent in advanced, complex IC designs.

Verification Group

Discovery Verification Platform.    Also during fiscal 2003, we introduced our Discovery^™ Verification Platform. The Discovery Platform combines many of our verification and nanometer level analysis tools in a unified environment to provide high performance and efficient interaction among these technologies. The Discovery Verification Platform includes the following products:

The Discovery Verification Platform also includes our Discovery AMS platform, a subset of the above technologies tuned to perform verification on analog and mixed analog-and-digital designs, and supports the latest Accellera SystemVerilog language standard, Verilog, VHDL, mixed-HDL, SystemC, and for analog mixed-signal based methodologies, Verilog-AMS and SPICE.

The increasing size and complexity of today’s ICs and SoCs have vastly increased the time and effort required to verify chip designs, with test creation and verification now consuming up to 70% of the total design time for a given IC. Our Discovery Platform combines our simulation and verification products and design-for-verification methodologies, and provides a consistent control environment to significantly improve the speed, breadth and accuracy of our customers’ verification efforts on complex chip designs, increasing their productivity and helping them deliver their products to market faster.

Solutions

    Synopsys’ Solutions Group includes our portfolio of IP products and components and our Consulting Services Group.

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Intellectual Property Products.    As IC designs continue to grow in size, reusing proven design blocks is an increasingly important way to reduce overall design cost and cycle time. Enabling reuse of IP requires a significant methodology shift from traditional IC design. In the past, designs were intimately tied to a particular semiconductor process technology or design methodology, making reuse of design blocks from one chip design to the next both difficult and costly. More recently, IC companies have been able to increasingly reuse pre-designed and verified IP components, particularly those that implement basic or standardized functions. The ability to reuse such IP allows IC companies to focus their design teams on designing the chip features that will give its products a competitive advantage. Using pre-designed IP can also reduce a chip designer’s verification risk by ensuring that the “designed in” portions of the chip are “pre-verified” and thus high quality. Because of the increasing importance of pre-designed IP, and in order to minimize the risk and effort in acquiring IP from a myriad of smaller suppliers, IC designers are beginning to consolidate their IP purchases from fewer vendors who can provide a reliable, comprehensive portfolio of proven IP.

Our IP products include:

Finally, Synopsys’ Star IP program permits DesignWare library users to gain access to popular microprocessor cores from leading semiconductor and IP companies. We have worked with these companies to improve the reusability of these microprocessor cores as well as to integrate them with other DesignWare microprocessor subsystems. The program includes cores from companies like MIPS, NEC and Infineon, and in 2003 we added a PowerPC microprocessor from IBM.

Professional Services.  We provide a comprehensive portfolio of consulting services covering all critical phases of the SoC development process, as well as systems development in wireless and broadband applications. We offer customers a variety of engagement models ranging from project assistance, which helps our customers design, verify and/or test their chips and improve their design processes, to full turnkey development.

New Ventures

Our New Ventures Group includes a number of products and initiatives relating to analog/mixed signal IC design and verification and design for manufacturing.

Analog Mixed-Signal Tools.  Our Cosmos^™ tool is used to create analog designs. Cosmos uses schematic-driven layout to place and route full-custom ICs. The New Ventures Group also manages development and marketing of our NanoSim and HSPICE tools described above under Discovery Verification Platform.

Design for Manufacturing.  With the acquisitions of Avant! and Numerical, we offer a variety of products and technologies used at the intersection of IC design and manufacturing which address a variety of issues, principally those encountered using photolithography techniques to manufacture ICs when advanced ICs have feature dimensions smaller than the wavelength of light used to expose those dimensions during production. We address these markets through our Design for Manufacturing initiatives, which include:

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Customer Service and Technical Support

We believe a high level of customer service and support is critical to the adoption and successful use of our products. We provide technical support for our products through both field- and corporate-based application engineering groups. Customers who purchase Technology Subscription Licenses (TSLs) receive software maintenance services, also known as “post contract support” (PCS), bundled with their license fee. Customers who purchase term licenses and perpetual licenses may purchase these services separately. See Product Sales and Licensing Agreements below.

Software maintenance services include minor product enhancements we develop, bug fixes and access to our technical support center for primary support. Software maintenance also includes access via electronic mail and the World Wide Web to SolvNet®, our web-based support solution that lets customers quickly seek answers to design questions or more insight into design problems. SolvNet gives customers access to Synopsys’ complete design knowledge database using sophisticated information retrieval technology. Updated daily, it includes documentation, design tips, and answers to user questions. Customers can also engage our application consultants, our worldwide network of product experts, for additional support needs.

Customer Education Services

We offer training workshops designed to increase customer design productivity while using our products. Workshops cover Synopsys tools and methodology used in our design and verification tool flows, as well as specialized modules addressing system design, logic design, physical design, simulation and test. We offer regularly scheduled workshops in Mountain View, California; Austin, Texas; Marlboro, Massachusetts; Reading, England; Rungis, France; Munich, Germany; Tokyo and Osaka, Japan; Seoul, Korea and other locations. We also schedule on-site workshops worldwide at our customers’ facilities or other locations. Approximately 8,500 engineers attended Synopsys workshops during fiscal 2003.

Product Warranties

We generally warrant our products to be free from defects in media and to substantially conform to material specifications for a period of 90 days. We also typically provide our customers limited indemnities with respect to claims that their use of our design and verification software products infringe on United States patents, copyrights, trademarks or trade secrets. We have not experienced material warranty or indemnity claims to date.

Support for Industry Standards

We actively create and support standards we believe will help our customers increase productivity, improve interoperability of tools from different vendors, and solve design problems. Standards in the EDA industry can be established by formal accredited committees, by licensing made available to all, or through open source licensing.

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Synopsys’ products support many formal standards, including the most commonly used hardware description languages, VHDL, Verilog HDL, SystemVerilog and SystemC, as well as numerous industry standard data formats for the exchange of data between our tools, other EDA vendor’s products and applications customers develop internally.

Synopsys is a board member and/or participant in the following major EDA standards organizations: Accellera, a not-for-profit formal standards organization that drives language-based standards for systems, semiconductor, and design tool companies; the interoperability committee of the EDA Consortium, which helps promote quality and interoperability among EDA products from different vendors; the Institute of Electrical and Electronics Engineers (IEEE), a non-profit, technical professional association and a leading developer of global industry standards; the Virtual Socket Interface Alliance (VSIA), an industry group formed to promote standards that facilitate the integration and reuse of functional blocks of intellectual property; and the Open SystemC Initiative (OSCI), a non-profit organization that manages SystemC, a language developed by Synopsys and donated to OSCI, with representation from the systems, semiconductor, IP, embedded software and EDA industries.

Synopsys’ TAP-in program provides interface standards to all companies through an open source licensing model. Synopsys manages changes and enhancements that come from the community of licensees. Synopsys, other EDA companies and EDA customers use these standards to facilitate interoperability of their tools. The standards offered through TAP-in include Liberty for library modeling, SDC for design constraints, SAIF for switching activity and OpenVera for hardware verification. Synopsys’ common database, Milkyway, is available for tool integration by EDA vendors through our MAP-in program.

Synopsys’ products are written mainly in the C and C++ languages and utilize industry standards for graphical user interfaces. Our software runs under UNIX operating systems, such as Solaris and HP-UX, and under the RedHat Linux operating system. Synopsys’ products are offered on the most widely used hardware platforms, including those from Sun Microsystems, Hewlett-Packard, IBM and PCs that are based upon Intel and AMD microprocessors.

Sales, Distribution and Backlog

We market our products and services primarily through direct sales and application engineers or support personnel in the United States and principal foreign markets. We employ highly skilled engineers and technically proficient sales persons in order to understand our customers’ needs and explain and demonstrate the value of our products.

In fiscal 2003, 2002 and 2001, foreign revenues represented 43%, 35% and 37%, respectively, of Synopsys’ total revenue. Additional information relating to domestic and foreign operations is contained in Note 9 of our Notes to Consolidated Financial Statements in Part II, Item 8. Financial Statements and Supplementary Data. Information relating to risks associated with foreign operations are described in Part II, Item 7, Management’s Discussion and Analysis of Financial Condition and Results of Operations—Factors That May Affect Future Results—Stagnation of foreign economies, foreign exchange rate fluctuations or other international issues could adversely affect our performance.

We have sales/support centers throughout the United States, in addition to our Mountain View, California headquarters. Outside the United States, we have sales/support offices in Canada, Denmark, Finland, France, Germany, Hong Kong, India, Israel, Italy, Japan, the Netherlands, the People’s Republic of China, Singapore, South Korea, Sweden, Switzerland, Taiwan and the United Kingdom. Our foreign headquarters is in Dublin, Ireland. Our offices are further described under Part I, Item 2, Properties.

In limited circumstances, we use distributors to assist us in the sale of certain products in specified markets. See Note 11 of our Notes to Consolidated Financial Statements in Part II, Item 8. Financial Statements and Supplementary Data for additional information about one of our distributors.

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Historically, orders and revenue have been lowest in our first fiscal quarter and highest in our fourth fiscal quarter, with a material decline between the fourth quarter of one fiscal year and the first quarter of the next fiscal year. We expect the first fiscal quarter will remain our lowest orders and revenue quarter; orders and revenue in other quarters will vary based on the particular timing and type of individual contracts entered into with large customers.

Synopsys’ aggregate non-cancelable backlog was approximately $1.6 billion on November 1, 2003, representing a 17% increase from the end of the prior fiscal year. Aggregate non-cancelable backlog includes deferred revenue, operational backlog and financial backlog and excludes all items relating to consulting services. Deferred revenue represents orders for software products, license maintenance and other services which have been delivered and billed to the customer but the revenue has not yet been earned. Operational backlog consists of orders for system and software products sold under perpetual or term licenses and TSLs with customer requested ship dates within three months which have not been shipped. Financial backlog consists of future installments to be billed and received from the customer not yet currently due and payable. In the case of a TSL, financial backlog includes the full amount of the committed non-cancelable order, less any amount of revenue that has been recognized on such TSL.

We have not historically experienced significant order cancellations.

Research and Development

Our future performance depends in large part on our ability to further integrate our design and verification platforms, maintain and enhance our current products, develop new products, and meet an expanding range of customer requirements. Research and development on existing and new products is primarily conducted within each business unit. Synopsys also maintains an Advanced Technology Group, which is responsible for exploring new technologies and maintaining strong research relationships outside Synopsys within both industry and academia.

During fiscal 2003, 2002 and 2001, research and development expenses, net of capitalized software development costs, were $285.9 million, $225.5 million and $189.8 million, respectively. Synopsys capitalized software development costs were approximately $2.6 million, $1.6 million and $1.0 million in fiscal 2003, 2002 and 2001, respectively. We anticipate that we will continue to commit substantial resources to research and development in the future.

Manufacturing

Synopsys’ manufacturing operations consist of packaging and shipping CD-ROMs containing software products and the related documentation. We currently conduct these activities through contract vendors, who provide the majority of CD-ROM replication and on-demand printing and distribution of product media and documentation. We deliver an increasing proportion of our software products by electronic means rather than by shipping disks. When specified by the customer or required by law, Synopsys delivers disks to the customer’s site. We typically deliver our software products within 10 days of acceptance of customer purchase orders and execution of software license agreements unless the customer requests otherwise.

Competition

The EDA industry is highly competitive. We compete against other EDA vendors and against our customers’ own design tools and internal design capabilities. In general, we compete on product quality and features, post-sale support, interoperability with other vendors’ products, price, payment terms and, as discussed below, the ability to offer a complete design flow.

Our competitors include companies that offer a broad range of products and services, such as Cadence Design Systems, Inc. (Cadence) and Mentor Graphics Corporation, and companies that offer products focused on

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a discrete phase or phases of the integrated circuit design process. During the recent semiconductor downturn, we have increasingly competed on the basis of payment terms and price. During fiscal 2003, we increasingly agreed to extended payment terms on our TSLs, negatively affecting our deferred revenue and cash flow from operations. In addition, in certain situations our competitors offer aggressive discounts on their products. As a result, average prices may fall, and we may lose potential business where we believe a given discount is not in our best interests.

Increasingly, EDA companies compete on the basis of design flows involving integrated logic and physical design products rather than on the basis of individual point tools performing a discrete phase of the design process. The need to offer an integrated design flow will become increasingly important as ICs grow more complex. While we have introduced design and verification platforms that integrate many of the products required to design an IC into a unified flow, we face significant competition from companies that also offer their own integrated design flows, such as Cadence and Magma Design Automation, Inc. To be successful in the future, we believe we must further integrate our design and verification products, which will continue to require significant engineering and development work. There can be no guarantee that we will be able to offer a competitive complete design flow to customers. If customers fail to adopt our design and verification platforms or if we are unable to develop new discrete design tools or enhance existing ones to add increased functionality or performance, our financial condition and results of operations will be materially and adversely affected.

Product Sales and Licensing Agreements

We typically license our software to customers under non-exclusive license agreements that transfer title to the media only and restrict use to specified purposes within specified geographical areas. The majority of our licenses are network licenses that allow a number of individual users to access the software on a defined network. License fees depend on the type of license, product mix and number of copies of each product licensed. In certain cases, customers have the right to use our products over a wide-area network or to exchange a portion of the software under license for different software products of equal value.

We currently offer our software products under three license types: renewable TSLs, renewable term licenses, and perpetual licenses. For a full discussion of these licenses, see Part II, Item 7, Management’s Discussion and Analysis of Financial Condition and Results of Operations—Critical Accounting Policies—Revenue Recognition below.

With respect to our DesignWare Core intellectual property products, we typically license those products to our customers under nonexclusive license agreements which provide usage rights for specific applications. Fees under these licenses are typically charged on a per design basis plus, in some cases, royalties.

Finally, our professional services teams typically operate under consulting agreements with our customers with statements of work specific to each project.

Proprietary Rights

Synopsys primarily relies upon a combination of copyright, patent, trademark and trade secret laws and license and nondisclosure agreements to establish and protect its proprietary rights. Our source code is protected both as a trade secret and as an unpublished copyrighted work. However, third parties may develop similar technology independently. In addition, effective copyright and trade secret protection may be unavailable or limited in certain foreign countries. We currently hold United States and foreign patents on some of the technologies included in our products and will continue to pursue additional patents in the future.

Under our customer agreements and other license agreements, in many cases we offer to indemnify our customer if the licensed products infringe on a third party’s intellectual property rights. As a result, we are from time to time subject to claims that our products infringe on these third party rights. For example, we are currently

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defending some of our customers against claims that their use of one of our products infringes a patent held by a Japanese electronics company. We believe this claim is without merit and will continue to vigorously pursue this defense.

These types of claims can result in costly and time-consuming litigation, require us to enter into royalty arrangements, subject us to damages or injunctions restricting our sale of products, require us to refund license fees to our customers or to forgo future payments or require us to redesign certain of our products, any one of which could materially and adversely affect our business.

Employees

As of November 1, 2003, Synopsys had 4,362 employees, of whom 2,885 were based in North America and 1,477 were based outside of North America. Our future financial results depend in part upon the continued service of our key technical and senior management personnel and our continuing ability to attract and retain highly qualified technical and managerial personnel. We participate in a dynamic industry, with start-up activity, and our headquarters is in Silicon Valley, where competition for the most highly skilled technical, sales and management employees is intense. Experience at Synopsys is highly valued in the EDA and general electronics industry, and our employees are recruited aggressively by our competitors and by start-up companies in many industries. We have periodically experienced significant employee turnover. We can provide no assurances that we can retain our key managerial and technical employees or continue to attract or retain additional highly qualified technical and managerial personnel in the future. None of our employees is represented by a labor union. We have experienced no work stoppages, and we believe our employee relations are good.

Item 2. Properties

Synopsys’ principal offices are located in four adjacent buildings in Mountain View, California, which together provide approximately 400,000 square feet of available space. This space is leased through February 2015. Within one half mile of these buildings, in Sunnyvale, California, Synopsys occupies approximately 200,000 square feet of space in two adjacent buildings, which are under lease through April 2007, and approximately 72,000 square feet of space in a third building, which is under lease through April 2007. We use these buildings for administrative, marketing, research and development and support activities. In addition, Synopsys leases 16,000 square feet of space in Pleasanton and Fremont, California as telecommute centers. As a result of fiscal 2002 and 2003 acquisitions, we assumed leases of approximately 55,000 square feet of space in San Jose, California, 7,500 square feet of space in Pleasanton and 5,000 square feet of space in Austin, Texas, none of which we currently occupy.

Synopsys owns two buildings totaling approximately 230,000 square feet on approximately 43 acres of land in Hillsboro, Oregon, which we use for administrative, marketing, research and development and support activities. In addition, we lease approximately 80,000 square feet of space in Marlboro, Massachusetts for sales and support, research and development and customer education activities. This facility is leased through January 2009.

Synopsys owns a fourth building in Sunnyvale, California with approximately 120,000 square feet, which is leased to a third party through February 2009. Synopsys also owns 34 acres of undeveloped land in San Jose, California and 13 acres of undeveloped land in Marlboro, Massachusetts.

Synopsys currently leases 32 other offices throughout the United States primarily for sales and support.

Synopsys leases approximately 45,000 square feet in Dublin, Ireland for its foreign headquarters and for research and development purposes. This space is leased through April 2026. In addition, Synopsys leases 34 foreign sales and service offices in Canada, Denmark, Finland, France, Germany, Hong Kong, India, Israel, Italy, Japan, the Netherlands, the People’s Republic of China, Singapore, South Korea, Sweden, Switzerland, Taiwan

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and the United Kingdom. We also lease research and development facilities in Canada, France, Germany, India, Ireland, Japan, Korea, the Netherlands, the People’s Republic of China, South Korea, Sweden, Taiwan and the United Kingdom.

We believe our properties are adequately maintained and suitable for their intended use and that our facilities have adequate capacity for our current needs.

Item 3. Legal Proceedings

Synopsys is currently a party to various claims and legal proceedings which arise in the ordinary course of business. If management believes a loss arising from these actions is probable and can reasonably be estimated, we record the amount of the loss or the minimum estimated liability when the loss is estimated using a range and no point within the range is more probable than another. As additional information becomes available, we assess any potential liability related to these actions and revise our estimates, if necessary. Based on currently available information, management believes the ultimate outcome of these actions, individually and in the aggregate, will not have a material adverse effect on our financial position or overall trends in results of operations. However, litigation is inherently uncertain, and we could therefore receive unfavorable rulings. An unfavorable ruling could include monetary damages or an injunction prohibiting Synopsys from selling one or more products. An unexpected unfavorable ruling could have a material adverse impact on our results of operations for the period in which the ruling occurs or future periods.

Item 4. Submission of Matters to a Vote of Security Holders

No matters were submitted for a vote of security holders during the fourth quarter of fiscal 2003.

Executive Officers of the Registrant

The executive officers of Synopsys and their ages as of December 31, 2003, are:

Dr. Aart J. de Geus co-founded Synopsys and currently serves as Chief Executive Officer and Chairman of the Board of Directors. Since the inception of Synopsys in December 1986, he has held a variety of positions including Senior Vice President of Engineering and Senior Vice President of Marketing. From 1986 to 1992,

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Dr. de Geus served as Chairman of the Board. He served as President from 1992 to 1998. Dr. de Geus has served as Chief Executive Officer since January 1994 and has held the additional title of Chairman of the Board since February 1998. He has served as a Director since 1986. From 1982 to 1986, Dr. de Geus was employed by General Electric Corporation, where he was the Manager of the Advanced Computer-Aided Engineering Group. Dr. de Geus holds an M.S.E.E. from the Swiss Federal Institute of Technology in Lausanne, Switzerland and a Ph.D. in electrical engineering from Southern Methodist University.

Dr. Chi-Foon Chan joined Synopsys as Vice President of Application Engineering & Services in May 1990. Since April 1997 he has served as Chief Operating Officer and since February 1998 he has held the additional title of President. Dr. Chan also became a Director of Synopsys in February 1998. From September 1996 to February 1998 he served as Executive Vice President, Office of the President. From February 1994 until April 1997 he served as Senior Vice President, Design Tools Group and from October 1996 until April 1997 as Acting Senior Vice President, Design Re-Use Group. Additionally, he has held the titles of Vice President, Engineering and General Manager, DesignWare Operations and Senior Vice President, Worldwide Field Organization. From March 1987 to May 1990, Dr. Chan was employed by NEC Electronics, where his last position was General Manager, Microprocessor Division. From 1977 to 1987, Dr. Chan held a number of senior engineering positions at Intel Corporation. Dr. Chan holds an M.S. and a Ph.D. in computer engineering from Case Western Reserve University.

Steven K. Shevick joined Synopsys in July 1995 and currently serves as Senior Vice President, Finance and Chief Financial Officer. Mr. Shevick was appointed Senior Vice President and Chief Financial Officer in January 2003. From October 1999 to January 2003, he was Vice President, Investor Relations and Legal and Corporate Secretary. From March 1998 to October 1999, he was Vice President, Legal, General Counsel and Assistant Corporate Secretary. From July 1995 to March 1998 he served as Deputy General Counsel and Assistant Corporate Secretary. Mr. Shevick holds an A.B. from Harvard College and a J.D. from Georgetown University Law Center.

Vicki L. Andrews joined Synopsys in May 1993 and currently serves as Senior Vice President, Worldwide Sales. Before holding that position, she served in a number of senior sales roles at Synopsys, including Vice President, Global and Strategic Sales, Vice President, North America Sales and Director, Western United States Sales. She has more than 18 years of experience in the EDA industry. Ms. Andrews holds a B.S. in biology and chemistry from the University of Miami.

Dr. Raul Camposano has served as Senior Vice President and Chief Technology Officer since September 2000. Prior to that time, he was our Senior Vice President, General Manager of the Design Tools Group from 1997 through September 2000. Prior to joining Synopsys in 1994, he directed the Design Technology Institute at the German National Research Center for Computer Science (GMD) and was a professor in the Department of Computer Science at the University of Paderborn, Germany. Between 1986 and 1991, Dr. Camposano worked at the IBM T.J. Watson Research Center. He was also a member of the research staff at the Computer Science Research Laboratory at the University of Karlsruhe. Dr. Camposano received a B.S.E.E. degree in 1977 and a diploma in electrical engineering in 1978 from the University of Chile and a Ph.D. in computer science from the University of Karlsruhe in 1981.

John Chilton has served as Senior Vice President and General Manager of the Solutions Group of Synopsys since August 2003. Prior to that time, he was our Senior Vice President and General Manager of the IP and Design Services Business Unit from 2001 to August 2003. From 1997 to 2001, Mr. Chilton served as Vice President and General Manager of the Design Reuse Business Unit. Mr. Chilton received an M.S.E.E. from the University of Southern California and a B.S.E.E. from University of California at Los Angeles.

Janet S. Collinson has served as Senior Vice President, Human Resources and Facilities since August 2003. From September 1999 to August 2003 she was our Vice President, Real Estate and Facilities. Prior to that time she served as Director of Facilities from January 1997 to September 1999. Ms. Collinson received a B.S. in Human Resources from California State University, Fresno.

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Dr. Antun Domic has served as Senior Vice President and General Manager of the Implementation Group since August 2003. Prior to that, Dr. Domic was Vice President and General Manager of the Nanometer Analysis and Test Group from 1999 to August 2003. Dr. Domic joined Synopsys in April 1997, having previously worked at Cadence Design Systems and Digital Equipment Corporation. Dr. Domic has a B.S. in Mathematics and Electrical Engineering from the University of Chile in Santiago, Chile, and a Ph.D. in Mathematics from the Massachusetts Institute of Technology.

Manoj Gandhi has served as Senior Vice President and General Manager, Verification Group since August 2000. Prior to that he was Vice President and General Manager of the Verification Tools Group from July 1999 to August 2000. Prior to that time, he was Vice President of Engineering from December 1997 until July 1999. He holds a B.S. in Computer Science and Engineering from the Indian Institute of Technology, Kharagpur and an M.S. in Computer Science from the University of Massachusetts, Amherst.

Deirdre Hanford has served as Senior Vice President of Worldwide Applications Services since December 2002. Prior to that time, she was Senior Vice President, Business and Market Development of Synopsys from September 1999 to December 2002. From October 1998 until September 1999, she served as Vice President Sales for Professional Services and prior to that as Vice President, Corporate Applications Engineering from April 1996 to September 1999. Ms. Hanford received a B.S.E.E. from Brown University and an M.S.E.E. from University of California at Berkeley. Ms. Hanford sits on the board of directors of Joint Venture Silicon Valley, an industry advocacy group, and the American Electronics Association’s national board of directors.

Sanjiv Kaul has served as the Senior Vice President of the New Ventures Group since July 2003. Prior to that he was Senior Vice President of Corporate Applications and Marketing from October 2002 to July 2003. From 1998 until July 2003, Mr. Kaul headed our IC Implementation business unit. He joined Synopsys in April 1995. Mr. Kaul holds a B.S. degree from the University of Delhi, India and a B.S.E.E. from the University of Maryland. He has also done graduate work at Santa Clara University.

Rex S. Jackson joined Synopsys in February 2003 as Vice President, General Counsel and Corporate Secretary. Prior to joining Synopsys, Mr. Jackson was an investment director with Redleaf Group, Inc., an early stage venture capital firm, from April 2000 through December 2001, and President and CEO of Atlantes Services, Inc., a Redleaf portfolio company, from December 2001 through February 2003. Prior to joining Redleaf, from August 1998 to April 2000, Mr. Jackson was Vice President and General Counsel of AdForce, Inc., a provider of ad management and delivery services on the Internet. Prior to joining AdForce, Mr. Jackson served as Vice President, Business Development and General Counsel of Read-Rite Corporation, a manufacturer of thin film recording heads for the disk and tape drive industries from 1996 to 1998 and as Vice President and General Counsel from 1992 to 1996. Mr. Jackson holds an A.B. degree from Duke University and a J.D. degree from Stanford University.

There are no family relationships among any Synopsys executive officers or directors.

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PART II

Item 5. Market for Registrant’s Common Equity and Related Stockholder Matters

The table below sets forth information regarding repurchases of Synopsys common stock by Synopsys during the fiscal quarter ended October 31, 2003.

All shares were purchased pursuant to a $500 million stock repurchase program approved by Synopsys’ Board of Directors on December 9, 2002. Effective December 3, 2003, the Board of Directors renewed the program and increased the authorized funds to $500 million, not including amounts expended prior to such date. Funds are available until expended or until the program is suspended by the Chief Financial Officer or the Board of Directors.

The remaining information required by Item 5 is set forth in Note 13 of our Notes to Consolidated Financial Statements in Part II, Item 8, Financial Statements and Supplementary Data.

Item 6. Selected Financial Data

Financial Summary

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Item 7. Management’s Discussion and Analysis of Financial Condition and Results of Operations

The following discussion of our financial condition and results of operations should be read in conjunction with our Consolidated Financial Statements and the related “Notes to Consolidated Financial Statements” in Item 8, and “Financial Statements and Supplementary Data” in this Annual Report on Form 10-K. This discussion contains forward-looking statements within the meaning of Section 21E of the Securities Exchange Act of 1934. Our actual results could differ materially from those projected in the forward-looking statements as a result of a number of factors, risks and uncertainties, including the risk factors set forth in this discussion, especially under the caption “Factors That May Affect Future Results,” and elsewhere in this Form 10-K. Generally, the words “may,” “will,” “could,” “would,” “anticipate,” “expect,” “intend,” “believe,” “continue,” or the negatives of such terms, or other comparable terminology and similar expressions identify forward-looking statements. The information included in this Form 10-K is as of the filing date with the Securities and Exchange Commission and future events or circumstances could differ significantly from the forward-looking statements included herein. Accordingly, we caution readers not to place undue reliance on such statements.

Overview

The following is a summary of the discussion of our financial condition and results of operations and is qualified in its entirety by the fuller discussion contained in this Item 7. This summary should be read in conjunction with Part I, Item 1, “Business” and is qualified in its entirety by the risk factors set forth in Item 7 as described below under “Factors That May Affect Future Results.”

Synopsys is the world leader in electronic design automation (EDA) software used to design complex integrated circuits (ICs) and systems-on-chips (SoCs) in the global semiconductor and electronics industries. Our software and intellectual property products and design services provide a complete IC design and verification solution from original concept to the actual chip, enabling our customers to bring advanced products to market quickly. See “Item 1, Business” for a more complete description of our business.

Business Environment

As an EDA software provider, we generate substantially all of our revenues from the semiconductor and electronics industries. Our customers typically fund purchases of our software and services out of their research and development budgets. As a result, our revenues are heavily influenced by our customers’ long-term business outlook, and willingness to invest in new chip designs.

Beginning in late calendar 2000, the semiconductor industry entered its steepest and longest downturn of the past 20 years, with industry sales dropping by approximately 46% from late 2000 to early 2002. As a result, over the past three years our customers have focused on controlling costs and reducing risk, including constraining R&D expenditures, cutting back on their design starts, purchasing from fewer suppliers, requiring more favorable pricing and payment terms from those suppliers and pursuing consolidation within their own industry. Further, during this downturn, many start-up semiconductor design companies failed or were acquired, and the pace of investment in new companies declined.

In response to these conditions, we have focused on providing the most technologically advanced products to address each step in the IC design process, on integrating these products into broad platforms, and on expanding our product offerings. Our goal is to be the EDA technology supplier of choice for our customers as they pursue longer-term, broader, more flexible relationships with fewer suppliers. Reflecting this trend, in fiscal 2003 we signed 11 new contracts over $25 million, up from only three in fiscal 2001.

While the semiconductor industry experienced a moderate recovery in 2003, our customers have remained cautious. It is therefore not yet clear when improved demand in our own customers’ electronics end markets will cause them to significantly increase their R&D spending or their design starts, and hence their spending on EDA.

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Product Developments

As the result of a multi-year strategy based upon focused internal development efforts and selective acquisitions, we offer our customers a comprehensive, end-to-end design flow. Our suite of system design, logic design, functional verification, physical design and physical verification products enables our customers to take an IC from concept all the way to manufacturing.

Following the completion of the Avant! merger in mid-2002, we moved quickly to integrate our operations and research and development teams. We have also pursued integration of the products themselves. In February 2003, we announced the combination of many of our leading IC design products into a single, unified platform called the Galaxy Design Platform, which now includes seven of our twelve highest revenue products: Design Compiler, Apollo/Astro, Physical Compiler, PrimeTime, Hercules, STAR-RCXT and DFT Compiler. Concurrently with this announcement, we also opened access to our Milkyway design database, which provides a common data repository and improves interoperability among multiple products. Enabling customers and other EDA tool vendors to link their tools directly into the Milkyway environment will benefit customers and other EDA companies by reducing integration costs and advancing tool interoperability for the electronics industry.

We also announced our Discovery Verification Platform in fiscal 2003, which combines many of our verification and nanometer level analysis tools in a unified environment to provide high performance and efficient interaction among these technologies, and includes three of our twelve highest revenue products: VCS, HSPICE and NanoSim.

Finally, in March 2003 we completed our acquisition of Numerical Technologies, Inc., which specializes in sub-wavelength photolithography-enabling solutions, expanding our offerings of manufacturing technologies and products geared towards small geometry designs.

Financial Performance

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Acquisitions

In fiscal 2003, we completed (i) our acquisition of Numerical Technologies, Inc. (Numerical) to expand our offerings of design for manufacturing products and (ii) two other acquisitions we do not consider material for financial statement purposes.

In fiscal 2002, we acquired: (i) Avant! Corporation (Avant!), a leading developer of software used in the physical design and physical verification phases of IC design; (ii) Co-Design Automation, Inc. (Co-Design), a developer of simulation software used in the high-level verification stage of the chip design process; and (iii) inSilicon Corporation (inSilicon), which developed, marketed and licensed an extensive portfolio of silicon intellectual property.

Our results of operations include the revenues attributable to products acquired in these mergers that are recognized after the respective merger dates but not any revenues recognized by these acquired companies prior to their respective merger dates. In addition, these acquisitions caused us to incur charges related to these acquisitions, such as amortization of goodwill, intangible assets and deferred stock compensation, and integration, as more fully discussed below.

Critical Accounting Policies

We base the discussion and analysis of our financial condition and results of operations upon our audited consolidated financial statements, which we prepare in accordance with accounting principles generally accepted in the United States of America. In preparing these financial statements, we must make estimates and judgments that affect the reported amounts of assets, liabilities, revenues and expenses and related disclosure of contingent assets and liabilities. On an on-going basis, we evaluate our estimates based on historical experience and various other assumptions we believe are reasonable under the circumstances. Our actual results may differ from these estimates.

The accounting policies that most frequently require us to make estimates and judgments, and therefore are critical to understanding our results of operations, are:

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Revenue Recognition.    Our revenue recognition policy is detailed in Note 2 of our Notes to Consolidated Financial Statements in Part II, Item 8. Financial Statements and Supplementary Data. We have designed and implemented revenue recognition policies in accordance with Statement of Position (SOP) 97-2, Software Revenue Recognition, as amended by SOP 98-9, Modification of SOP 97-2, Software Revenue Recognition, With Respect to Certain Transactions, and SOP 98-4, Deferral of the Effective Date of a Provision of SOP 97-2, Software Revenue Recognition.

With respect to software sales, Synopsys utilizes three license types:

We report revenue in three categories: upfront license revenue, time-based license revenue and services.

Upfront license revenue includes:

Time-based license revenue includes:

Services revenue includes:

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We allocate revenue on software transactions (referred to as an “arrangement” in the accounting literature) involving multiple elements to each element based on the relative fair values of the elements. Our determination of fair value of each element in multiple element arrangements is based on vendor-specific objective evidence (VSOE). We limit our assessment of VSOE for each element to the price charged when the same element is sold separately.

We have analyzed all of the elements included in our multiple-element arrangements and determined that we have sufficient VSOE to allocate revenue to the maintenance components of our perpetual and term license products and to consulting. Accordingly, assuming all other revenue recognition criteria are met, we recognize revenue from perpetual and term licenses upon delivery using the residual method in accordance with SOP 98-9 and recognize revenue from maintenance ratably over the maintenance term.

Customers occasionally request the right to convert their existing TSLs to perpetual licenses. Customers pay an incremental fee to convert the TSL to a perpetual license, which we recognize upon contract signing, in accordance with AICPA Technical Practice Aid (TPA) 5100.74, assuming all other revenue recognition criteria have been met. In some situations, the contract converting the TSL to a perpetual license is modified to such an extent that a new arrangement exists. The changes to the contract may include increases or decreases in the total technology under license, changes in payment terms, changes in license terms and other pertinent factors. In these situations, we account for all of the arrangement fees as a new sale and recognize revenue when all other revenue recognition criteria have been met. We have a policy that defines the specific circumstances under which such transactions are accounted for as a new perpetual license sale.

We make significant judgments related to revenue recognition. Specifically, in connection with each transaction involving our products, we must evaluate whether: (i) persuasive evidence of an arrangement exists, (ii) delivery has occurred, (iii) our fee is fixed or determinable, and (iv) collectibility is probable. We apply these criteria as discussed below.

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Valuation of Intangible Assets.    We evaluate our intangible assets for indications of impairment whenever events or changes in circumstances indicate that the carrying value may not be recoverable. Intangible assets consist of purchased technology, contract rights intangibles, customer-installed base/relationships, trademarks and tradenames, covenants not to compete, customer backlog and capitalized software. Factors that could trigger an impairment review include significant under-performance relative to expected historical or projected future operating results, significant changes in the manner of our use of the acquired assets or the strategy for our overall business or significant negative industry or economic trends. If this evaluation indicates that the value of the intangible asset may be impaired, we make an assessment of the recoverability of the net carrying value of the asset over its remaining useful life. If this assessment indicates that the intangible asset is not recoverable, based on the estimated undiscounted future cash flows of the acquired entity or technology over the remaining amortization period, we will reduce the net carrying value of the related intangible asset to fair value and may adjust the remaining amortization period. Any such impairment charge could be significant and could have a material adverse effect on our reported financial statements. We did not record any impairment charges on our intangible assets during fiscal 2003. As of October 31, 2003, the carrying amount of our intangible assets, net was $285.6 million.

We evaluate goodwill on a quarterly basis for indications of impairment based on our fair value as determined by our market capitalization in accordance with Statement of Financial Standards No. 142 (SFAS 142), Goodwill and Other Intangible Assets. If this evaluation indicates that the value of the goodwill may be impaired, we make an assessment of the impairment of the goodwill using the two-step method prescribed by SFAS 142. Any such impairment charge could be significant and could have a material adverse effect on our reported financial statements. We did not record any impairment charges on our goodwill during fiscal 2003. As of October 31, 2003, the carrying amount of our goodwill, net was $550.7 million.

Income Taxes.    The relative proportions of our domestic and foreign revenue and income directly affect our effective tax rate. We are also subject to changing tax laws in the multiple jurisdictions in which we operate. As of October 31, 2003, current net deferred tax assets and long-term liabilities totaled $248.4 million and $7.4 million, respectively. We believe it is more likely than not that our results of future operations will generate sufficient taxable income to utilize our net deferred tax assets. We consider future taxable income and ongoing prudent and feasible tax planning strategies in assessing the need for any valuation allowance, and if we determine we would not be able to realize all or part of our net deferred tax assets in the future, we would charge to income an adjustment to the deferred tax assets in the period we make that determination.

We provide for United States (U.S.) income taxes on the earnings of our foreign subsidiaries unless they are considered permanently invested outside of the United States. As of October 31, 2003, the cumulative amount of earnings upon which United States income taxes have not been provided is approximately $176.7 million. As of October 31, 2003, the unrecognized deferred tax liability for these earnings was approximately $49.1 million.

Allowance for Doubtful Accounts.    We estimate the collectibility of accounts receivable on an account-by-account basis and establish a specific reserve for any particular receivable when we determine collectibility is not probable. In addition, we provide a general reserve on all accounts receivable, which we calculate as a percentage, determined within a specified range of percentages of the outstanding balance in each aged group. In determining this percentage, we specifically analyze accounts receivable and historical bad debt expense, customer creditworthiness, current economic trends, international exposures (such as currency devaluation), and changes in our customer payment terms to evaluate the adequacy of the allowance for doubtful

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accounts. If the financial condition of our customers deteriorates, impairing their ability to make payments, we may need to establish additional allowances. As of October 31, 2003, our allowance for doubtful accounts was $8.3 million.

Strategic Investments.    We review our investments in non-public companies on a quarterly basis and estimate the amount of any impairment incurred during the current period based on a specific analysis of each investment, considering the activities of and events occurring at each of the underlying portfolio companies during the quarter. Our portfolio companies operate in industries that are rapidly evolving and extremely competitive. For equity investments in non-public companies where we cannot readily determine market value, we assess each investment for indicators of impairment at each quarter end based primarily on achievement of business plan objectives and current market conditions, among other factors, and information available to us at the time of assessment. The primary business plan objectives we consider include achievement of planned financial results, completion of capital raising activities, the launching of technology, the hiring of key employees and the portfolio company’s overall progress on its business plan. If we determine an investment in a portfolio company is impaired, absent quantitative valuation metrics, management estimates the impairment and/or the net realizable value of the portfolio investment based on public- and private-company market comparable information and valuations completed for companies similar to our portfolio companies. Future adverse changes in market conditions, poor operating results of underlying investments and other information obtained after our quarterly assessment could result in additional losses or an inability to recover the current carrying value of the investments thereby requiring a further impairment charge in the future. As of October 31, 2003, we valued our strategic investments at $8.6 million.

Results of Operations

Synopsys generates revenue primarily from licensing its software and intellectual property, from sales of maintenance, and from providing consulting services. In our licensing activities, to respond to our customers’ respective technology, flexibility and budget requirements, we have offered a variety of license types. We generally classify those license types as TBLs on which revenue is recognized over time, and upfront licenses on which revenue is recognized at the time of product shipment. These license types vary significantly in terms of access to technology, duration, flexibility and payment terms. See Critical Accounting Policies—Revenue Recognition above for a full discussion of our types of licenses and services and the revenue recognition associated with each.

Prior to the fourth quarter of fiscal 2000, we principally licensed our software via perpetual licenses and upfront term licenses, with the license revenue typically recognized upfront at the time the order was received and maintenance recognized ratably over the maintenance term. In the fourth quarter of fiscal 2000, we introduced Time Subscription Licenses. Since we bundle products and maintenance in TSLs, we generally recognize both product and service TSL revenue ratably over the term of the license, or, if later, as payments become due. As a result, a TSL order results in significantly lower current-period revenue than an equal-sized order for a perpetual or upfront term license. Conversely, a TSL order will result in higher revenues recognized in future periods than an equal-sized order for a perpetual or upfront term license. For example, for a $120,000 order for a perpetual or upfront term license, we recognize $120,000 of revenue in the quarter the product is shipped and no revenue in future quarters. For a $120,000 order for a 3-year TSL shipped on the first day of the quarter, we recognize $10,000 of revenue in the quarter the product is shipped and in each of the 11 succeeding quarters.

Because we generally recognize revenue on TSLs ratably over the TSL term, our reported revenue dropped significantly following our adoption of TSLs in the fourth quarter of fiscal 2000. In each quarter since adoption, however, our ratable revenue has grown as TSL orders we receive each quarter contribute revenue that is “layered” over the revenue ratably recognizable from TSL orders we received in prior quarters. As the TSL model matures, growth in ratable revenue in any quarter will depend on revenue derived from new TSL orders

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received in the quarter, offset by the loss of revenue from TSLs that expire in such quarter or the prior quarter, which cease to contribute to revenue. Due to the “layering” effect, revenue may grow from quarter to quarter for some time even if orders do not grow. The complete phase-in period of the TSL model is difficult to predict, as it is affected by mergers and acquisitions and by the precise mix of TSL orders received. We expect, however, that when the TSL model is fully phased in over the long term, revenue growth should track orders growth on a percentage basis.

Our license revenue in any given quarter depends upon the volume of upfront licenses shipped during the quarter, the amount of TBL revenue recognized from TBLs booked in prior periods, and to a much smaller degree, the amount of revenue recognized on TBL orders booked during the quarter. We set our revenue targets based in large part on orders targets and our expected mix of perpetual licenses, term licenses and TSLs for a given period. If we achieve the total order target but not our target license mix, we may not reach our revenue targets (if upfront license orders are lower than we expect), or may exceed them (if upfront license orders are higher than we expect). If we achieve the target license mix but orders are below target, then we will not meet our revenue targets.

The precise mix of orders can fluctuate substantially from quarter to quarter. Our historical license order mix since adopting TSLs in August 2000 has been 24% upfront licenses and 76% time-based licenses, although the percentage of upfront license orders in any given quarter has been as high as 33% and as low as 14%. The license mix for the fourth quarter of fiscal 2003 was 33% upfront and 67% time-based as compared to 27% upfront and 73% time-based for the same period in fiscal 2002.

Revenue.    Revenue consists of fees for upfront and time-based licenses of our software and intellectual property products, maintenance, customer training and consulting. We classify revenue as upfront license, time-based license or services. Upfront license revenue consists primarily of perpetual and upfront term software licenses. Time-based license revenue consists of revenue from our TSLs and from term licenses which have extended payment terms as discussed above. Service revenue consists of maintenance under perpetual and term licenses and fees for consulting services and training.

Total revenue for fiscal 2003 increased 30% to $1,177.0 million as compared to $906.5 million in fiscal 2002. The increase in total revenue for fiscal 2003 is primarily due to (i) contribution of Avant! products for a full fiscal year, (ii) continued phase-in of the TSL model and (iii) license renewals with many of our largest Japanese customers in the second quarter of fiscal 2003, a relatively high proportion of which were perpetual licenses. In the fourth quarter of fiscal 2003, we reintroduced term licenses. Total revenue from term licenses in fiscal 2003 was $3.6 million.

Total revenue for fiscal 2002 increased 33% to $906.5 million as compared to $680.4 million for fiscal 2001. The increase in total revenue for fiscal 2002 as compared to fiscal 2001 is due primarily to the contribution of Avant! products from June 2002 through the end of fiscal 2002 and to the ongoing phase in of the TSL license model.

Upfront license revenue for fiscal 2003 increased 22% to $298.3 million as compared to $245.2 million in fiscal 2002. The increase in upfront license revenue is primarily due to the contribution of Avant! products for a full fiscal year and license renewals with many of our largest Japanese customers in the second quarter of fiscal 2003, a relatively high proportion of which were perpetual licenses. During the second quarter of fiscal 2002, we began offering to some of our customers that entered into perpetual licenses in excess of $2 million variable maintenance arrangements under which the annual maintenance fee is calculated as a percentage of the net license fee rather than as a fixed percentage of the list price. These arrangements accounted for $220.0 million of our product sales in fiscal 2003 as compared to $131.6 million in fiscal 2002.

Upfront license revenue for fiscal 2002 increased 50% to $245.2 million as compared to $163.9 million for fiscal 2001. The increase in upfront license revenue for fiscal 2002 as compared to fiscal 2001 was due to an

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increase in perpetual licenses delivered during the period, which resulted in large part from the increased volume of perpetual licenses after the Avant! merger.

Time-based license revenue for fiscal 2003 increased 65% to $618.0 million as compared to $373.6 million in fiscal 2002. The increase in time-based license revenue is due to the additional quarters that the TSL license model has been used and to the increased volume of time-based license sales contributed by Avant! products for a full fiscal year.

Time-based license revenue for fiscal 2002 increased 114% to $373.6 million as compared to $174.6 million in fiscal 2001. The increase in ratable license revenue for fiscal 2002 compared to fiscal 2001 was due to the additional quarters that the TSL license model has been used and to the increased volume of ratable license sales resulting from the Avant! merger.

Service revenue for fiscal 2003 decreased 9% to $260.7 million as compared to $287.7 million in fiscal 2002. Service revenue for fiscal 2002 decreased 16% to $287.7 million as compared to $341.8 million for fiscal 2001. These decreases in service revenue were primarily due to the impact of our adoption of TSLs, which bundle maintenance with the software and do not contribute any separately recognized service revenue. Further, economic conditions led our customers to reduce their costs by curtailing their use of outside consultants such as our professional services personnel, and, in some cases, discontinuing maintenance on their perpetual licenses. In addition, customers deferred or cancelled a number of projects in our consulting backlog and reduced certain expenditures on training. And finally, our adoption of variable maintenance perpetual arrangements in fiscal 2002 has substantially lowered our maintenance fees from perpetual licenses.

Related Party Transactions.    Revenues derived from Intel Corporation and its subsidiaries in the aggregate accounted for approximately 9.5% and 7.9% of fiscal 2003 and 2002 revenues, respectively. Andy D. Bryant, Intel Corporation’s Executive Vice President and Chief Financial and Enterprise Services Officer, also serves on our Board of Directors. Management believes the transactions between the two parties were carried out on an arm’s length basis.

Revenue Seasonality.    Historically, orders and revenue have been lowest in our first fiscal quarter and highest in our fourth fiscal quarter, with a material decline between the fourth quarter of one fiscal year and the first quarter of the next fiscal year. We expect the first fiscal quarter will remain our lowest orders and revenues quarter; orders and revenues in other quarters will vary based on the particular timing and type of individual contracts entered into with large customers.

Revenue—Product Groups.    For management reporting purposes, we organize our products and services into five distinct groups: Galaxy Design Platform, Discovery Verification Platform, Intellectual Property (IP), New Ventures and Professional Services & Other. The following table summarizes the revenue attributable to these groups as a percentage of total revenue for the last twelve quarters. We include revenue from companies or products we have acquired during the periods covered from the acquisition date through the end of the relevant periods. For presentation purposes, we allocate maintenance, which represented approximately 18% of our total revenue and approximately 84% of our total services revenue for fiscal 2003, to the products to which those support services relate. Further, with the adoption of our platform strategy in fiscal 2003, we redefined our product groups and have reclassified prior period revenues in accordance with this new grouping to provide a consistent presentation.

Between any two quarters, the percentage of our total revenue from each group fluctuates based on the mix of upfront versus time-based orders received for these products during the quarter. Further, since our adoption of TSLs in the fourth quarter of fiscal 2000, an increasing percentage of the revenue in a given quarter in the Galaxy Design Platform, Discovery Verification Platform and New Ventures groups is from customer orders placed in preceding quarters. Accordingly, for the Galaxy Design Platform, Discovery Verification Platform and New Ventures groups, quarter-to-quarter changes are not necessarily indicative of fundamental strength or weakness in those groups.

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Galaxy Design Platform.    Our Galaxy Design Platform includes our logic synthesis, physical synthesis, physical design, timing analysis, signal integrity analysis and physical verification products. Our principal products in this category at October 31, 2003 were Design Compiler, Apollo, Astro, Physical Compiler, Prime Time, Hercules, Star RXCT and DFT Compiler.

Revenue for this platform increased significantly in percentage and absolute dollar terms following the Avant! merger in the third quarter of fiscal 2002, primarily because this product group represented the largest portion of Avant!’s revenue before the acquisition. The percentage increase in the second quarter of fiscal 2003 was due to a number of large orders, many of which were perpetual licenses, by Japanese customers in that quarter. Going forward, we believe physical implementation, physical synthesis and design analysis products will account for an increasing share of Galaxy Design Platform revenues relative to our logic synthesis products as customers recognize the importance of using physical level and design analysis tools to address design challenges particular to small geometry designs.

Discovery Verification Platform.    Our Discovery Verification Platform includes our verification and simulation products. Our principal products in this category are VCS, HSPICE, NanoSim, Formality, Vera and System Studio. Though the Avant! merger added few verification products, revenue for this platform as a percentage of total revenue has remained fairly consistent, reflecting continued adoption of these tools by our customers. In absolute dollar terms, revenue from this platform has generally increased consistently with our overall averages.

Intellectual Property.    Our IP products include the DesignWare library of IC design components and verification models and inSilicon products we acquired in September 2002. IP revenue as a percentage of total revenue decreased beginning in the third quarter of fiscal 2002 principally because we acquired few IP products in the Avant! merger, but increased beginning in the third quarter of fiscal 2003 due to increased sales of our DesignWare cores and products acquired in the inSilicon merger, particularly in the communications and connectivity areas.

New Ventures.    Our New Ventures products include our analog and mixed signal and design for manufacturing tools. We had no revenue from these tools prior to the third quarter of fiscal 2002, when we acquired Avant!. New Ventures revenue as a percentage of total revenue has since increased moderately primarily as a result of the growing need for tools and methodologies required for smaller geometry designs, and has increased in absolute dollar terms consistently with our overall averages.

Professional Services & Other.    The Professional Services Group provides consulting services, including design methodology assistance, specialized systems design services, turnkey design and training. As a percentage of total revenue, revenue from this product group declined significantly through the second quarter of fiscal 2003, reflecting a decrease in consulting orders from our customers due to difficult economic conditions as discussed above under Revenue, and the fact that Avant! did not have a significant professional services business.

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Workforce Realignment.    During the fourth quarter of fiscal 2003, we decided to realign our operations, effective in the first quarter of fiscal 2004, in order to focus resources on more strategic areas of investment and to become more operationally efficient. This realignment affected a total of approximately 240 employees (140 in the U.S. and 100 outside the U.S.) in all departments in domestic and foreign locations. The associated charge for fiscal 2003 was $14.9 million consisting of severance and other termination benefits, which are generally much higher in locations outside the U.S., and is reflected in the consolidated statement of income as follows:

We expect to incur additional costs between $3 million and $4 million during the first and second quarters of fiscal 2004 related to the consolidation of excess facilities and to the termination of certain lease obligations.

Temporary Shutdown of Operations.    During the third quarter of fiscal 2003, we had a four-day shutdown of operations in North America as a cost-saving measure. The savings relates primarily to salaries and benefits as follows:

Work Force Reduction.    We reduced our workforce during the first quarter of fiscal 2003 and the second quarter of fiscal 2002. The purpose was to reduce expenses by decreasing the number of employees in all departments in domestic and foreign locations. As a result, we decreased our workforce by approximately 200 and 175 employees during the first quarter of fiscal 2003 and the second quarter of fiscal 2002, respectively. The associated charge for fiscal 2003 was $4.4 million as compared to $3.9 million for fiscal 2002. The charge consists of severance and other termination benefits and is reflected in the consolidated statements of income as follows:

Cost of Revenue.    Cost of revenue consists of the cost of product revenue, cost of service revenue, cost of ratable license revenue and amortization of intangible assets and deferred stock compensation. Cost of product revenue includes personnel and related costs, production costs, product packaging, documentation and

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amortization of capitalized software development costs and purchased technology. Cost of service revenue includes consulting services, personnel and related costs associated with providing training and maintenance on perpetual and term licenses. Cost of ratable license revenue includes the costs of product and services related to our TSLs. Cost of product revenue, cost of service revenue and cost of ratable license revenue during any period are heavily dependent on the mix of software orders received during such period.

Cost of revenue amortization of intangible assets and deferred stock compensation includes the amortization of the contract rights intangible associated with certain executory contracts and the amortization of core/ developed technology related to acquisitions which occurred in fiscal 2003 and 2002. There was no cost of revenue amortization of intangible assets and deferred stock compensation in fiscal 2001. Total amortization of intangible assets and deferred stock compensation included in cost of revenues is as follows:

Total cost of revenue as a percentage of total revenue for fiscal 2003 increased to 20% as compared to 19% in fiscal 2002. This increase is primarily due to an increase in amortization of contract rights intangible and core/developed technology recorded as a result of our acquisitions in fiscal 2003 and 2002, the cost of our realignment of operations totaling $2.6 million as discussed above under Workforce Realignment, additional royalties of $1.5 million and other termination benefits of $1.2 million as discussed above under Work Force Reduction. Our total product costs are relatively fixed and do not fluctuate significantly with changes in revenue or changes in revenue recognition methods.

Total cost of revenue as a percentage of total revenue for fiscal 2002 remained relatively flat at 19% as compared to fiscal 2001. Cost of revenue, excluding amortization of intangible assets and deferred stock compensation, as a percentage of total revenue decreased due to the increase in quarterly amortization of deferred revenue and backlog, which is an inherent result of the use of the ratable license model until fully phased in and due to the fact that other cost of revenue components remained relatively flat. However, this decrease as a percentage of total revenue in fiscal 2002 was offset by the commencement of amortization of the contract rights intangible and core/developed technology recorded as a result of acquisitions in fiscal 2002.

Research and Development.    Research and development expenses for fiscal 2003 increased 27% to $285.9 million as compared to $225.5 million in fiscal 2002. The increase consists primarily of (i) $30.7 million in research and development personnel and related costs as a result of acquisitions in fiscal 2002 and 2003 and including additional employer payroll taxes incurred as a result of an increase in the number of stock option exercises during the fiscal year; (ii) $22.2 million in increased human resources, information technology and facilities costs to research and development as a result of the increase in research and development headcount as a percentage of total headcount; (iii) $6.3 million as a result of our realignment of operations as discussed above under Workforce Realignment; and (iv) $2.3 million in consulting services. These increases are partially offset by a decrease in depreciation expense of $2.8 million.

Research and development expenses for fiscal 2002 increased 19% to $225.5 million as compared to $189.8 million for fiscal 2001. The increase in expenses is due to increases of (i) $28.7 million in compensation and compensation-related costs as a result of an increase in research and development headcount due to the Avant! merger; (ii) $11.3 million in human resources, technology and facilities costs as a result of increased research and

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development staffing; and (iii) $4.2 million in depreciation expense. These increases were partially offset by decreases of (i) $5.4 million in consulting expenses and (ii) $4.3 million of other expenses including facilities, travel, communications, supplies and recruiting as a result of our cost reduction programs.

Sales and Marketing.    Sales and marketing expenses for fiscal 2003 increased 17% to $310.7 million as compared to $264.8 million in fiscal 2002. The increase consists primarily of (i) $42.4 million in additional sales and marketing personnel and related costs as a result of acquisitions in fiscal 2002 and 2003 and including additional employer payroll taxes incurred as a result of an increase in the number of stock option exercises during the fiscal year offset by savings from a four-day shutdown of operations in North America; (ii) $4.8 million as a result of our realignment of operations as discussed above under Workforce Realignment; and (iii) $2.7 million in additional travel expenses. These increases were partially offset by a decrease of $3.8 million in human resources, technology and facilities costs to sales and marketing expenses as a result of a decrease in sales and marketing headcount as a percentage of total headcount.

Sales and marketing expenses for fiscal 2002 decreased 3% to $264.8 million as compared to $274.0 million in fiscal 2001. The overall decrease is due to decreases of (i) $8.4 million in human resources, technology and facilities costs as a result of a decrease in sales and marketing headcount as a percentage of total headcount; (ii) $1.3 million in employee functions; (iii) $1.4 million in consulting expenses; and (iv) $2.8 million in other expenses including communications and supplies, foundation contributions, professional services, subscriptions and memberships as a result of our cost reduction efforts. These decreases were partially offset by increases of (i) $4.8 million in compensation and related costs attributable to an increase in sales and marketing headcount resulting from the Avant! merger and (ii) $1.9 million in travel relating to customer visits to discuss the integration of Synopsys and Avant! products.

General and Administrative.    General and administrative expenses for fiscal 2003 increased 15% to $90.0 million as compared to $78.5 million in fiscal 2002. The increase consists primarily of (i) $12.8 million in additional general and administrative personnel and related costs as a result of acquisitions in fiscal 2002 and 2003 and including additional employer taxes incurred as a result of an increase in the number of stock option exercises during the current year; (ii) $7.0 million in depreciation on upgrades to our information technology infrastructure; (iii) $5.7 million in facilities costs due to new leases during the current year and the expiration of a sublease on one of Synopsys’ buildings in June 2003; (iv) $3.7 million in professional services costs, patent prosecution expenditures, Sarbanes-Oxley Act compliance and litigation; (v) $2.8 million in maintenance agreements covering more software and computing equipment due to acquisitions in fiscal 2002 and 2003; and (vi) $1.2 million related to the realignment of operations as discussed above under Workforce Realignment. These increases were offset by a decrease of (i) $14.2 million in human resources, technology and facilities costs to general and administrative expenses as a result of a decrease in general and administrative headcount as a percentage of total headcount; and (ii) a decrease of $6.6 million in bad debt expense as accounts receivable aging improved year over year.

General and administrative expenses for fiscal 2002 increased 13% to $78.5 million as compared to $69.7 million in fiscal 2001. The overall increase is due to increases of (i) $11.1 million in facilities costs as a result of an increased number of sites due to the Avant! merger; (ii) $7.0 million in compensation and compensation-related costs as a result of increased headcount due to the Avant! merger; (iii) $5.6 million in professional service fees; (iv) $2.2 million in communications costs; (v) $1.6 million in equipment to update licenses for our internal enterprise application systems; (vi) $1.4 million in depreciation; and (vii) $2.9 million in other expenses including travel and property tax assessments. These increases were offset by decreases of (i) $20.0 million as a result of decreased general and administrative headcount as a percentage of total headcount and (ii) $3.9 million in consulting costs as a result of our cost reduction efforts.

Integration Costs.    Non-recurring integration costs incurred relate to merger activities which are not included in the purchase consideration under Emerging Issues Task Force Number 95-3 (EITF 95-3), Recognition of Liabilities in Connection with a Purchase Business Combination. These costs are expensed as

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incurred. During fiscal 2002, integration costs were $128.5 million and consisted primarily of (i) $95.0 million related to the premium for the insurance policy acquired in conjunction with the Avant! merger; (ii) $14.7 million related to write-downs of Synopsys facilities and property under the management approved facility exit plan for the Avant! merger; (iii) $10.0 million and $0.7 million related to severance costs for Synopsys employees who were terminated and costs associated with transition employees as a result of the Avant! and inSilicon mergers, respectively; (iv) $1.3 million related to the write-off of software licenses owned by Synopsys which were originally purchased from Avant!; (v) $3.7 million goodwill impairment charge related to a prior Synopsys acquisition as a result of the acquisition of Avant!; and (vi) $1.2 million and $1.9 million of other expenses including travel and certain professional fees for the Avant! and Co-Design mergers, respectively.

In-Process Research and Development.    Purchased in-process research and development (IPRD) of $19.9 million and $87.7 million in fiscal 2003 and 2002, respectively, represents the write-off of in-process technologies associated with our acquisitions of Numerical in fiscal 2003 and Avant! and inSilicon in fiscal 2002. There were no acquisitions during fiscal 2001. At the date of each acquisition, the projects associated with the IPRD efforts had not yet reached technological feasibility and the research and development in process had no alternative future uses. Accordingly, these amounts were charged to expense on the respective acquisition dates of each of the acquired companies.

Valuation of IPRD.    The value assigned to acquired in-process technology is determined by identifying products under research in areas for which technological feasibility had not been established. The value of in-process technology is then segmented into two classifications: (i) developed technology (completed) and (ii) in-process technology (to-be-completed), giving explicit consideration to the value created by the research and development efforts of the acquired business prior to the date of acquisition and to be created by Synopsys after the acquisition. These value creation efforts were estimated by considering the following major factors: (i) time-based data, (ii) cost-based data and (iii) complexity-based data.

The value of the in-process technology was determined using a discounted cash flow model similar to the income approach, focusing on the income producing capabilities of the in-process technologies. Under this approach, the value is determined by estimating the revenue contribution generated by each of the identified products within the classification segments. Revenue estimates were based on (i) individual product revenues, (ii) anticipated growth rates, (iii) anticipated product development and introduction schedules, (iv) product sales cycles, and (v) the estimated life of a product’s underlying technology. From the revenue estimates, operating expense estimates, including costs of sales, general and administrative, selling and marketing, income taxes and a use charge for contributory assets, were deducted to arrive at operating income. Revenue growth rates were estimated by management for each product and gave consideration to relevant market sizes and growth factors, expected industry trends, the anticipated nature and timing of new product introductions by us and our competitors, individual product sales cycles and the estimated life of each product’s underlying technology. Operating expense estimates reflect Synopsys’ historical expense ratios. Additionally, these projects will require continued research and development after they have reached a state of technological and commercial feasibility. The resulting operating income stream was discounted to reflect its present value at the date of acquisition.

The rate used to discount the net cash flows from purchased in-process technology is our weighted-average cost of capital (WACC), taking into account our required rates of return from investments in various areas of the enterprise and reflecting the inherent uncertainties in future revenue estimates from technology investments including the uncertainty surrounding the successful development of the acquired in-process technology, the useful life of such technology, the profitability levels of such technology, if any, and the uncertainty of technological advances, all of which are unknown at this time.

Numerical.    On March 1, 2003, we acquired Numerical, which specialized in subwavelength lithography-enabling solutions. The IPRD expense related to the Numerical acquisition was $18.3 million. Numerical had five IPRD projects—Phase Shift Masking (PSM), Subwavelength Software, Equipment Software, Cadabra and Computer Aided Transcription System (CATS)—representing 25%, 7%, 6%, 5% and 57%, respectively, of the total

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IPRD value. These projects were expected to be completed shortly following the completion of the merger. PSM, Subwavelength Software and CATS were completed in fiscal 2003. Cadabra was released in the first quarter of fiscal 2004. The Equipment Software project consists of in-process technology for multiple products. These products were either completed in fiscal 2003, discontinued or are expected to be integrated with other Synopsys products during fiscal 2004. Expenditures to complete Numerical’s IPRD approximate the original estimates.

inSilicon.    On September 20, 2002, we acquired inSilicon, a leading provider of connectivity semiconductor intellectual property used by semiconductor and systems companies to design systems-on-chip that are critical components of innovative wired and wireless products. The IPRD expense related to the inSilicon acquisition was $5.2 million. inSilicon had three IPRD projects—DELA, Peripheral Component Interconnect (PCI) Express and Universal Serial Business Physical (USB PHY)—accounting for 54%, 23% and 23% of the total IPRD value, respectively. These projects were 25%, 67% and 20% complete at the time of acquisition, respectively. During fiscal 2003, Synopsys decided to no longer pursue the DELA project. PCI Express is approximately 80% complete and USB PHY has been completed. Expenditures to complete USB PHY and expected expenditures to complete PCI Express approximate the original estimates.

Avant!.    On June 6, 2002, we acquired Avant!, a leading developer of software used in the physical design and physical verification stages of IC design. The IPRD expense related to the Avant! merger was $82.5 million. The principal in-process technologies were identified based on the following product families:

These projects were completed during fiscal 2002 and 2003. Expenditures to complete the acquired in-process technologies approximated the original estimates.

The risks associated with acquired research and development are considered high and no assurance can be made that these products will generate any benefit to us or meet market expectations.

Amortization of Goodwill, Intangible Assets and Deferred Stock Compensation.    Amortization of intangible assets and deferred stock compensation includes the amortization of trademarks, tradenames, customer relationships and covenants not to compete and is included in operating expenses as follows:

The increase in amortization of intangible assets is due primarily to fiscal 2003 and 2002 acquisitions partially offset by a decrease in goodwill amortization as a result of the adoption of SFAS 142 on November 1, 2002.

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The following table presents the estimated future amortization of deferred stock compensation reported in both cost of revenue and operating expenses:

Impairment of Intangible Assets.    In fiscal 2002, we recognized an aggregate impairment charge of $3.8 million to reduce the amount of certain intangible assets associated with prior acquisitions to their estimated fair value. Approximately $3.7 million and $0.1 million are included in integration expense and amortization of intangible assets, respectively, on the consolidated statement of operations. The impairment charge is primarily attributable to certain technology acquired from and goodwill related to the acquisition of Stanza, Inc. (Stanza) in 1999. During fiscal 2002, we determined that we would not allocate future resources to assist in the market growth of this technology as products acquired in the merger with Avant! provided customers with superior capabilities. As a result, we do not anticipate any future sales of the Stanza product.

In fiscal 2001, we recognized an aggregate impairment charge of $2.2 million to reduce the amount of certain intangible assets associated with prior acquisitions to their estimated fair value. Approximately $1.8 million and $0.4 million are included in cost of revenues and amortization of intangible assets, respectively, on the consolidated statement of operations. The impairment charge is attributable to certain technology acquired from and goodwill related to the acquisition of Eagle Design Automation, Inc. (Eagle) in 1997. During fiscal 2001, we determined that we would not allocate future resources to assist in the market growth of this technology. As a result, we do not anticipate any future sales of the Eagle product.

There were no impairment charges during fiscal 2003.

Other (Expense) Income, Net.    Other income, net was $24.1 million in fiscal 2003 and consisted primarily of (i) realized gain on investments of $20.7 million; (ii) rental income of $6.3 million; (iii) interest income of $5.2 million; (iv) impairment charges related to certain assets in our venture portfolio of ($4.5) million; (vii) foundation contributions of ($2.1) million; and (viii) interest expense of ($1.6) million.

Other (expense), net of other income was ($208.6) million in fiscal 2002 and consisted primarily of (i) ($240.8) million expense due to the settlement of the Cadence Design Systems, Inc. (Cadence) litigation; (ii) ($11.3) million in impairment charges related to certain assets in our venture portfolio; (iii) realized gains on investments of $22.7 million; (iv) a gain of $3.1 million for the termination fee on the IKOS Systems, Inc. (IKOS) merger agreement; (v) rental income of $10.0 million; (vi) interest income of $8.3 million; and (vii) and other miscellaneous expenses including amortization of premium forwards and foreign exchange gains and losses recognized during the fiscal year of ($0.6) million.

Other income, net was $83.8 million in fiscal 2001 and consisted primarily of (i) a gain of $10.6 million on the sale of our silicon libraries business to Artisan Components, Inc.; (ii) ($5.8) million in impairment charges related to certain assets in our venture portfolio; (iii) realized gains on investments of $55.3 million; (iv) rental income of $8.6 million; (v) interest income of $12.8 million; and (vi) other miscellaneous income including amortization of premium forwards and foreign exchange gains and losses recognized during the fiscal year of $2.3 million.

Termination of Agreement to Acquire IKOS Systems, Inc.    On July 2, 2001, we entered into an Agreement and Plan of Merger and Reorganization (the IKOS Merger Agreement) with IKOS Systems, Inc. The IKOS Merger Agreement provided for the acquisition of all outstanding shares of IKOS common stock by Synopsys.

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On December 7, 2001, Mentor Graphics Corporation (Mentor) commenced a cash tender offer to acquire all of the outstanding shares of IKOS common stock at $11.00 per share, subject to a number of conditions. On March 12, 2002, Synopsys and IKOS executed a termination agreement by which the parties terminated the IKOS Merger Agreement and pursuant to which IKOS paid Synopsys the $5.5 million termination fee required by the IKOS Merger Agreement. This termination fee and $2.4 million of expenses incurred in conjunction with the acquisition are included in other income, net on the consolidated statement of operations for the year ended October 31, 2002. Synopsys subsequently executed a revised termination agreement with Mentor and IKOS in order to add Mentor as a party thereto.

Effect of New Accounting Standards

In July 2001, the Financial Accounting Standards Board (FASB) issued Statements of Financial Accounting Standards No. 142, Goodwill and Other Intangible Assets. We adopted SFAS 142 on November 1, 2002 and ceased amortizing goodwill recorded for business combinations consummated prior to July 1, 2001. In addition, as of November 1, 2002, we assessed the useful lives and residual values of all acquired intangible assets recorded on the balance sheet and also tested goodwill for impairment per SFAS 142. In our impairment analysis, we determined we have one reporting unit. We completed the goodwill impairment review as of the beginning of fiscal 2003 and found no indicators of impairment. This impairment review was based on our fair value as determined by our market capitalization. As of October 31, 2003, unamortized goodwill was $550.7 million, which, in accordance with SFAS 142, we will not amortize.

Liquidity and Capital Resources

Cash, cash equivalents and short-term investments increased $283.6 million, or 68%, to $698.4 million as of October 31, 2003 from $414.7 million as of October 31, 2002. Our source of cash, cash equivalents and short-term investments over the last three years has been from funds generated from our business, including cash on hand from companies we have acquired.

Cash provided by operations was $391.5 million in fiscal 2003 as compared to cash used by operations of $181.0 million in fiscal 2002. Cash flow in fiscal 2002 reflected the payment of $335.8 million in insurance premiums related to settlement of litigation between Avant!, which we acquired in June 2002, and Cadence, resulting in a net loss for the year. Cash provided by operations is directly related to the payment terms we grant on sales of our software and services. During fiscal 2003, we have increasingly granted extended payment terms to our customers, negatively affecting cash flow from operations. Cash flow from operations in 2003 reflected a significant cash tax benefit resulting form the net loss in fiscal 2002. During fiscal 2003 cash was provided by net income adjusted for non-cash related items, for cash flows related to hedging activities and by an increase in deferred revenue due to continued sales of TSLs. Cash used for changes in working capital balances included decreases in accounts payable, accrued liabilities and accounts receivable. Accounts payable and accrued liabilities decreased as a result of payments of merger-related accruals, commissions and year-end bonuses, partially offset by current year accruals. Accounts receivable decreased due to the timing of installment billings to customers on long-term arrangements.

Cash used in investing activities was $258.3 million in fiscal 2003 as compared to cash provided by investing activities of $275.7 million in fiscal 2002. During fiscal 2003, the following occurred: (i) cash paid for acquisitions totaled $167.7 million; (ii) net purchases of short- and long-term investments totaled $37.8 million; and (iii) capital expenditures totaled $50.1 million. In fiscal 2002, the following occurred: (i) cash received from acquisitions totaled $168.3 million; (ii) proceeds from net sales of investments totaled $157.8 million; and (iii) capital expenditures totaled $48.8 million.

Cash provided by financing activities was $74.2 million in fiscal 2003 as compared to cash used in financing activities of $51.8 million in fiscal 2002. The increase of $126.0 million in cash provided by financing activities is primarily due to an increase in proceeds of $215.1 million from the sale of shares pursuant to our

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employee stock option plans during fiscal 2003 offset by an increase in the purchase of treasury stock. During fiscal 2003, Synopsys repurchased treasury stock of $260.7 million as compared to $171.7 million in fiscal 2002.

Accounts receivable, net of allowances, decreased $6.2 million, or 3%, to $201.0 million as of October 31, 2003 from $207.2 million as of October 31, 2002. Days sales outstanding, calculated based on revenues for the most recent quarter and accounts receivable at the balance sheet date, decreased to 58 days as of October 31, 2003 from 61 days as of October 31, 2002. The decrease in days sales outstanding is due in part to the timing of large cash collections realized during the fourth quarter of fiscal 2003.

On November 22, 2002 and December 16, 2002, we made payments to Cadence totaling $20.0 million and $245.0 million, respectively, under the terms of the settlement agreement relating to litigation between Cadence and Avant!. See Note 3 of our Notes to Consolidated Financial Statements in Part II, Item 8. Financial Statements and Supplementary Data.

On March 1, 2003, we completed our acquisition of Numerical Technologies, Inc. We paid Numerical common stock holders $7.00 in cash in exchange for each share of Numerical common stock owned as of the merger date, or approximately $240.2 million in total and $161.3 million net of cash held by Numerical at the merger date. We paid for Numerical common stock out of our cash, cash equivalents and short-term investments.

We believe that our current cash, cash equivalents, short-term investments and cash generated from operations will satisfy our business requirements for at least the next twelve months.

Stock Option Plans

Under our 1992 Stock Option Plan (the 1992 Plan), 38,951,016 shares of common stock have been authorized for issuance. Pursuant to the 1992 Plan, the Board of Directors (the Board) may grant either incentive or non-qualified stock options to purchase shares of common stock to eligible individuals at not less than 100% of the fair market value of those shares on the grant date. Stock options granted under the 1992 Plan generally vest over a period of four years and expire ten years from the date of grant. As of October 31, 2003, 9,003,784 stock options remain outstanding and 7,479,776 shares of common stock are reserved for future grants under this plan.

Under our 1998 Non-Statutory Stock Option Plan (the 1998 Plan), 53,247,068 shares of common stock have been authorized for issuance. Pursuant to the 1998 Plan, the Board may grant non-qualified stock options to employees, excluding executive officers. Exercisability, option price and other terms are determined by the Board but the option price shall not be less than 100% of the fair market value of those shares on the grant date. Stock options granted under the 1998 Plan generally vest over a period of four years and expire ten years from the date of grant. As of October 31, 2003, 28,161,720 stock options remain outstanding and 8,179,958 shares of common stock were reserved for future grants under this plan.

Under our 1994 Non-Employee Directors Stock Option Plan (the Directors Plan), 1,800,000 shares have been authorized for issuance. The Directors Plan provides for automatic grants to each non-employee member of the Board upon initial appointment or election to the Board, upon reelection and for annual service on Board committees. The option price shall not be less than 100% of the fair market value of those shares on the grant date. Under the Directors Plan, as originally adopted, new directors receive an option for 40,000 shares, vesting in equal installments over four years. In addition, each continuing director who is elected at an annual meeting of stockholders receives an option for 20,000 shares and an additional option for 10,000 shares for each Board committee membership, up to a maximum of two committee service grants per year. In August 2003, the Board amended the Directors Plan in order to reduce the size of the initial and committee grants to 30,000 and 5,000 shares, respectively. The annual and committee service option grants vest in full on the date immediately prior to the date of the annual meeting following their grant. In the case of directors appointed to the Board between annual meetings, the annual and any committee grants are prorated based upon the amount of time since the last annual meeting. As of October 31, 2003, 1,168,492 stock options remain outstanding and 110,346 shares of common stock were reserved for future grants under this plan.

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We have assumed certain option plans in connection with business combinations. Generally, the options granted under these plans have terms similar to our own options. The exercise prices of such options have been adjusted to reflect the relative exchange ratios. We do not intend to make future grants out of these option plans.

We monitor dilution related to our option program by comparing net option grants in a given fiscal period to the number of shares outstanding. The dilution percentage is calculated as the new option grants for the fiscal period, net of options forfeited by employees leaving Synopsys, divided by the total outstanding shares at the end of such fiscal period. The option dilution percentages were 0.9% and 3.4% for fiscal 2003 and 2002, respectively.

A summary of the distribution and dilutive effect of options granted is as follows:

A summary of our option activity and related weighted-average exercise prices for fiscal 2003 is as follows:

As of October 31, 2003, a total of approximately 39.0 million, 53.2 million and 1.8 million shares were reserved for issuance under our 1992, 1998 and Directors Plans, respectively, of which 15.8 million shares were available for future grants. For additional information regarding our stock option activity during fiscal 2002, please see Note 7 of our Notes to Consolidated Financial Statements in Part II, Item 8. Financial Statements and Supplementary Data.

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A summary of outstanding in-the-money and out-of-the-money options and related weighted-average exercise prices as of October 31, 2003 is as follows:

The following table sets forth further information regarding individual grants of options during fiscal 2003 for the Chief Executive Officer and each of the other four most highly compensated executive officers (named executive officers) serving as such on October 31, 2003 whose compensation for fiscal 2003 exceeded $100,000.

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The following table provides the specified information concerning exercises of options to purchase our common stock and the value of unexercised options held by our named executive officers as of October 31, 2003:

The following table provides information regarding equity compensation plans approved and not approved by security holders as of October 31, 2003:

Pre-approvals of Non-Audit Services by Audit Committee

Pursuant to Section 10A(i)(3) of the Exchange Act, during the fourth quarter of fiscal 2003, the Audit Committee pre-approved the following non-audit services to be performed by KPMG LLP, our independent auditors:

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Factors That May Affect Future Results

Weakness or budgetary caution in the semiconductor and electronics industries would negatively impact our business.

The semiconductor and electronics industries experienced steep declines in orders and revenue in 2001 and 2002, before recovering moderately in 2003. Further recovery is subject to significant risks, and these manufacturers have been cautious to adopt an improved outlook on demand for their products. Accordingly, they may continue to constrain their EDA investments, and we cannot predict whether, or when, further recovery will translate into increased EDA investments. Should our customers and prospective customers remain cautious in their EDA purchases due to market conditions or other factors, our business, operating results and financial condition would be materially and adversely affected.

The EDA industry is highly competitive, and competition may have a material adverse affect on our business and operating results.

We compete with other EDA vendors that offer a broad range of products and services, such as Cadence Design Systems and Mentor Graphics Corporation, and with EDA vendors that offer products focused on one or more discrete phases of the IC design process. We also compete with customers’ internally developed design tools and capabilities. If we fail to compete effectively our business will be materially and adversely affected.

We compete principally on technology leadership, product quality and features, post-sale support, interoperability with our own and other vendors’ products, price and payment terms. Additional competitive challenges include: