SECURITIES AND EXCHANGE COMMISSION

Washington, D.C 20549

 

FORM 10-K

Commission File Number: 0-18032

 

ý

ANNUAL REPORT PURSUANT TO SECTION 13 OR 15(d) OF THE SECURITIES EXCHANGE ACT OF 1934 FOR THE FISCAL YEAR ENDED DECEMBER 29, 2001

 

LATTICE SEMICONDUCTOR CORPORATION

(Exact name of Registrant as specified in its Charter)

 

Registrant’s telephone number, including area code: (503) 268-8000

 

Securities registered pursuant to Section 12(b) of the Act:  None

Securities registered pursuant to Section 12(g) of the Act:

 

 

 

                Indicate by check mark whether the Registrant (1) has filed all reports required to be filed by Section 13 or 15(d) of the Securities Exchange Act of 1934 during the preceding 12 months (or for such shorter period that the Registrant was required to file such reports), and (2) has been subject to such filing requirements for the past 90 days.

 

Yes ý  No o

 

                Indicate by check mark if disclosure of delinquent filers pursuant to Item 405 of Regulation S-K is not contained herein, and will not be contained, to the best of the Registrant’s knowledge, in definitive proxy or information statements incorporated by reference in Part III of this Form 10-K or any amendment to this Form 10-K.

 

Yes o  No ý

 

                As of March 15, 2002, the aggregate market value of the shares of voting stock of the Registrant held by non-affiliates was approximately $1.337 billion.  Shares of Common Stock held by each officer and director and by each person who owns 5% or more of the outstanding Common Stock have been excluded in that such persons may be deemed affiliates.  This determination of affiliate status is not necessarily a conclusive determination for other purposes.

 

                As of March 15, 2002, 109,635,440 shares of the Registrant’s common stock were outstanding.

 

DOCUMENTS INCORPORATED BY REFERENCE

 

                1.  Portions of the Annual Report to Stockholders for the fiscal year ended December 29, 2001 are incorporated by reference in Part II hereof.

 

                2.  Portions of the definitive proxy statement of the Registrant to be filed pursuant to Regulation 14A for the 2002 Annual Meeting of Stockholders to be held on May 7, 2002 are incorporated by reference in Part III hereof.

LATTICE SEMICONDUCTOR CORPORATION

FORM 10-K

ANNUAL REPORT

TABLE OF CONTENTS

 

Item of Form 10-K
PART I
Item 1	—	Business
Item 2	—	Properties
Item 3	—	Legal Proceedings
Item 4	—	Submission of Matters to a Vote of Security Holders
Item 4(a)	—	Executive Officers of the Registrant
PART II
Item 5	—	Market for the Registrant’s Common Stock and Related Stockholder Matters
Item 6	—	Selected Financial Data
Item 7	—	Management's Discussion and Analysis of Financial Condition and Results of Operations
Item 7(a)	—	Quantitative and Qualitative Disclosures About Market Risk
Item 8	—	Financial Statements and Supplementary Data
Item 9	—	Changes in and Disagreements with Accountants on Accounting and Financial Disclosure
PART III
Item 10	—	Directors and Executive Officers of the Registrant
Item 11	—	Executive Compensation
Item 12	—	Security Ownership of Certain Beneficial Owners and Management
Item 13	—	Certain Relationships and Related Transactions
PART IV
Item 14	—	Exhibits, Financial Statement Schedules and Reports on Form 8-K
Signatures
Report on Financial Statement Schedule
Financial Statement Schedule

 

1

 

 

Item 1.  Business.

 

BUSINESS

 

                 Lattice Semiconductor Corporation designs, develops and markets high performance programmable logic devices, or PLDs, and related software.  Programmable logic devices are widely-used semiconductor components that can be configured by end customers as specific logic circuits, and thus enable shorter design cycle times and reduced development costs.  Our end customers are primarily original equipment manufacturers in the communications, computing, industrial, military and consumer end markets.

 

                In January 2002, we acquired the field programmable gate array (“FPGA”) business of Agere Systems, Inc. (“Agere”). This acquisition increased our share of the PLD market, accelerated our entry into the FPGA segment and provided us with additional technical employees and intellectual property.  In 1999, we acquired Vantis Corporation (“Vantis”), the programmable logic device subsidiary of Advanced Micro Devices (“AMD”).  This acquisition also increased our share of the PLD market, accelerated development of new products and broadened our customer base.

 

Change in Fiscal Reporting Period

 

                We report based on a 52 or 53 week year ending on the Saturday closest to December 31. For ease of presentation, we have adopted the convention of using March 31, June 30, September 30 and December 31 as period end dates for all financial statement captions. In the fourth quarter of 1999, we changed our fiscal year end from March 31 to December 31. The nine month fiscal period ended January 1, 2000 is referred to as “the nine months ended December 31, 1999” or “fiscal period 1999.”

 

PLD Market Background

 

                Three principal types of digital integrated circuits are used in most electronic systems: microprocessors, memory and logic.  Microprocessors are used for control and computing tasks, memory is used to store programming instructions and data, and logic is employed to manage the interchange and manipulation of digital signals within a system.  Logic contains interconnected groupings of simple logical “and” and logical “or” functions, commonly described as “gates.”  Typically, complex combinations of individual gates are required to implement the specialized logic functions required for systems applications.  While system designers use a relatively small number of standard architectures to meet their microprocessor and memory needs, they require a wide variety of logic circuits in order to achieve end product differentiation.

 

                Logic circuits are found in a wide range of today’s digital electronic equipment including communication, computing, industrial, military and consumer systems.  According to World Semiconductor Trade Statistics, a semiconductor industry association, logic accounted for approximately 28% of the estimated $118 billion worldwide digital integrated circuit market in 2001.  The logic market encompasses, among other segments, standard logic, custom–designed application specific integrated circuits, or ASICs, which include conventional gate-arrays, standard cells and full custom logic circuits, and PLDs.

 

                Manufacturers of electronic equipment are challenged to bring differentiated products to market quickly.  These competitive pressures often preclude the use of custom–designed ASICs, which generally entail significant design risks, non-recurring costs and time delays.  Standard logic products, an alternative to custom–designed ASICs, limit a manufacturer’s flexibility to adequately customize an end system.  PLDs address this inherent dilemma.  PLDs are standard products, purchased by systems manufacturers in a “blank” state, that can be custom configured into a virtually unlimited number of specific logic functions by programming the device with electrical signals.  PLDs give system designers the ability to quickly create custom logic functions to provide product differentiation without sacrificing rapid time to market.  Certain PLD

 

2

 

products, including our own, are reprogrammable, meaning that the logic configuration can be modified, if needed, after the initial programming.  ISP^TM PLDs, pioneered by us, extend the flexibility of standard reprogrammable PLDs by allowing the system designer to configure and reconfigure logic functions using standard power supplies and without removing the PLD from the system board.

 

                According to Gartner, the PLD market was approximately $2.6 billion in 2001.  Within this market there are two main segments, complex PLD (“CPLD”) and FPGA, each representing a distinct silicon architectural approach.  In 2001, CPLD was a $0.7 billion market while FPGA was a $1.9 billion market.

 

                Products based on the two alternative PLD architectures are generally optimal for different types of logic functions, although many logic functions can be implemented using either architecture.  CPLDs are characterized by a regular building block structure of wide-input logic cells, called macrocells, and use of a centralized logic interconnect scheme.  FPGAs are characterized by a narrow–input logic cell and use a distributed interconnect scheme.  FPGAs may also contain dedicated blocks of fixed circuits such as memory, high-speed interface logic or processing engines.  Although CPLDs and FPGAs are typically suited for use in distinct types of logic applications, we believe that a substantial portion of PLD customers utilize both CPLD and FPGA architectures within a single system design, partitioning logic functions across multiple devices to optimize overall system performance and cost.

 

                A growing percentage of the PLD market is made up of devices that operate using 3.3–volt, or lower, power supplies.  Lower voltage PLDs benefit end users by consuming less power and providing compatibility with other advanced electronic components.

 

Technology

 

                We believe that our proprietary E²CMOS^â technology is the preferred process technology for CPLD products due to its inherent performance, reprogrammability and testability benefits.  E²CMOS technology, through its fundamental ability to be programmed and erased electronically, serves as the foundation for our ISP products.

 

                We pioneered the development of in–system programmability^TM which has become an industry standard feature in the PLD market.  Our ISP devices use either 5-volt or 3.3-volt programming signals and, as a result, can be configured and reconfigured by a system designer without being removed from the printed circuit board.  Standard E²CMOS PLDs require a 12-volt programming signal and therefore must be removed from the printed circuit board and programmed using specialized hardware.  Our ISP devices offer enhanced flexibility compared to standard PLDs and provide significant benefits to our customers.  Our ISP devices can allow customers to reduce design cycle times, accelerate time to market, reduce prototyping costs, reduce manufacturing costs and lower inventory requirements.  Our ISP devices can also provide customers the opportunity to perform simplified and cost-effective field reconfiguration through a data file transferred by computer disk or serial data signal.

 

Products

 

                We strive to offer innovative and differentiated programmable solutions based on our proprietary technology.

 

CPLD  Products

 

                Since 1992, we have focused on developing a leadership portfolio of CPLD products and increasing the percentage of our overall revenue derived from this attractive market.  During 2001, approximately 76% of our revenue was derived from CPLD products, as compared to 66% in calendar 1999 and essentially zero in 1992.  At present we offer the industry’s broadest line of CPLDs based on our 16 families of ispLSI^® and ispMACH^® products which include 75 devices.  In the future, we plan to continue to introduce new families of innovative CPLD products, as well as improve the performance and

 

3

 

reduce the manufacturing cost of our existing product families based on market needs.

 

                Our newest CPLD product families use innovative architectures and are targeted towards the low voltage portion of the market.  We believe that our multiple families of leadership CPLD products provide us a competitive advantage in this market.  The key features of these families are described in the table below:

 

 

FPGA  Products

 

                In 2002, we entered the FPGA market as a result of our acquisition of the FPGA business of Agere.  At present we offer over 40 FPGA devices within our three ORCA^Ò product families.  These  products are targeted toward the mainstream FPGA market.  In the future, we plan to introduce new families of innovative, high performance and higher density FPGAs.  Key features of our currently available FPGA families are described in the table below:

 

 

 

                In addition, we currently offer a groundbreaking new category of FPGA products called field programmable system chips (“FPSC”).  FPSCs, which combine generic FPGA logic and embedded intellectual property cores on a single programmable chip, offer customers the ability to quickly implement complex system-level designs in a flexible manner.  Currently, we offer four FPSC devices, the ORT82G5, ORT8850L, ORLI10G and ORLI12G, based on our ORCA 4 FPGA platform.  These devices incorporate high-speed interface protocols, offering up to 3.125 Gbs SERDES, and other application-specific circuit blocks that allow customers to develop high performance designs to implement 10 Gigabit ethernet and SONET applications within advanced communications systems.

 

                We also offer two additional product families, ispGDX and ispGDXV, that target a unique aspect of the programmable logic market.  These families extend in-system programmability to the circuit board level using an innovative digital cross–point switch architecture.  Offered with propagation delays as low as 3.5 nanoseconds, up to 240 input/output pins and complete pin-to-pin signal routing, both the 5-volt ispGDX and the 3.3-volt ispGDXV are targeted towards digital signal interconnect and interface applications.

 

Mixed Signal Products

 

                During 1999, we added mixed signal products to our portfolio as we believe these devices provide an opportunity to extend our proprietary technology to an untapped potential market.  Our five device ispPAC^® family extends in-system programmability to the analog market.  The innovative architecture of our ispPAC products allow designers to quickly and easily program resistor and capacitor values, gain and signal polarity and circuit interconnect to implement a wide variety of analog circuits.  Our initial ispPAC products are targeted towards filtering and signal conditioning applications and can

 

4

 

replace numerous discrete analog components.  ispPAC designs are implemented and programmed via a personal computer using our software development tool, PAC-Designer^®.

 

Software Development Tools

 

                All Lattice ISP products are supported by our new ispLEVER™ software development tool suite.  The ispLEVER software, our fifth generation design environment, features several important enhancements including a logic module generator, an improved constraints editor, HTML-based reporting and navigation and an automated update facility.  Supporting both the PC and UNIX platforms, ispLEVER allows our customers to enter, verify and synthesize a design, perform logic simulation and timing analysis, assign input/output pins, designate critical paths, debug, execute automatic timing-driven place and route tasks and download a program to one of our ISP devices.  Seamlessly integrated with third–party electronic design automation environments, ispLEVER provides a front-to-back design flow that leverages a customer’s prior investment in tools offered by Aldec, Cadence, Mentor Graphics, Synopsys and Synplicity.  In the future, we plan to continue to enhance and expand the capability of our software development tool suite.

 

                We also provide a variety of software algorithms that support in-system programming of our ISP devices through an interface cable or directly from a system microprocessor.

 

Low Density PLD Products

 

                We offer the industry’s broadest line of low-density CMOS PLDs based on our 18 families of GAL^® products offered in over 200 speed, power, package and temperature range combinations. These devices range in complexity from approximately 200 to 1,000 logic gates and are typically assembled in 20-, 24- and 28-pin standard dual in-line packages and in 20- and 28-pin standard plastic leaded chip carrier packages.  We offer the standard 16V8, 20V8 and 22V10 architectures in a variety of speed grades, with propagation delays as low as 3.5 nanoseconds, the highest performance in the industry.  In addition, we offer several proprietary extension architectures, the isp22V10, 6001/2, 16VP8, 16V8Z, 18V10, 20VP8, 20V8Z, 20RA10, 20XV10 and 26V12, each of which is optimized for specific applications.   We also offer a full range of 3.3-volt standard architectures, the isp22LV10, 16LV8, 20LV8, 22LV10 and 26CLV12, in a variety of speed grades, with propagation delays as low as 3.5 nanoseconds, the highest performance in the industry.

 

Product Development

 

                We place substantial emphasis on new product development and believe that continued investment in this area is required to maintain our competitive position.   Our product development activities emphasize new proprietary products, enhancement of existing products and process technologies and improvement of software development tools.  Product development activities occur in Hillsboro, Oregon; San Jose, California; Boulder, Colorado; Colorado Springs, Colorado; Naperville, Illinois; Allentown, Pennsylvania; Austin, Texas; Salt Lake City, Utah; Shanghai, China and Corsham, England.

 

                Research and development expenses were $45.9 million in fiscal period 1999, $77.1 million in 2000 and $71.7 million in 2001.  We expect to continue to make significant future investments in research and development.

 

Operations

 

                We do not manufacture our own silicon wafers.  We maintain strategic relationships with large semiconductor manufacturers to source our finished silicon wafers.  This strategy allows us to focus our internal resources on product, process and market development, and eliminates the fixed cost of owning and operating manufacturing facilities.  We are also able to take advantage of the ongoing advanced process technology dedicated development efforts of semiconductor manufacturers.  In addition, all of our assembly operations are performed by outside suppliers.  We perform certain test operations and reliability and quality assurance processes internally.  We have achieved an ISO 9001 quality certification, an

 

5

 

indication of our high internal operational standards.

 

Wafer Fabrication

 

                We source silicon wafers from our foundry partners, Seiko Epson in Japan, UMC in Taiwan and Chartered Semiconductor in Singapore, pursuant to agreements with each company and their respective affiliates.  We negotiate wafer volumes, prices and other terms with our foundry partners and their respective affiliates on a periodic basis.  We also source a small portion of our wafer requirements from AMD and Agere Systems in order to support ongoing manufacturing requirements for certain of our mature product lines we obtained as a result of our acquisitions.

 

Assembly

 

                After wafer fabrication and initial testing, we ship wafers to independent subcontractors for assembly.  During assembly, wafers are separated into individual die and encapsulated in plastic or ceramic packages.  Presently, we have qualified long-term assembly partners in China, Malaysia, the Philippines, Singapore, South Korea, Taiwan and Thailand.

 

Testing

 

                We electrically test the die on each wafer prior to shipment for assembly.  Following assembly, prior to customer shipment, each product undergoes final testing and quality assurance procedures.  Final testing on certain products is performed by independent contractors in China, Malaysia, the Philippines, South Korea, Singapore, Taiwan, Thailand and the United States.

 

Marketing, Sales and Customers

 

                We sell our products directly to end customers through a network of independent manufacturers’ representatives and indirectly through a network of independent distributors.  We also employ a direct sales management and field applications engineering organization to support our end customers and indirect sales resources.  Our end customers are primarily original equipment manufacturers in the communication, computing, industrial, military and consumer end markets.

 

                As of December 2001, we used 20 manufacturers’ representatives and two distributors, Arrow Electronics and Avnet, in North America.  We have also established export sales channels in over 30 foreign countries through a network of over 30 sales representatives and distributors.  Approximately one-half of our North American sales and the majority of our export sales are made through distributors.

 

                We protect each of our North American distributors and some of our foreign distributors against reductions in published prices, and expect to continue this policy in the foreseeable future.  We also allow returns from these distributors of unsold products under certain conditions.  For these reasons, we do not recognize revenue until products are resold by these distributors to an end customer.

 

                We provide technical and marketing support to our end customers with engineering staff based at our headquarters, design centers and selected field sales offices. We maintain numerous domestic and international field sales offices in major metropolitan areas.

 

                Export sales as a percentage of our total revenue were 53% in fiscal period 1999, 57% in 2000 and 54% in 2001.  Both export and domestic sales are denominated in U.S. dollars, with the exception of sales to Japan, which are dominated in yen.  If our export sales decline significantly there would be a material adverse impact on our business and results of operations.

 

6

 

                Our products are sold to a large and diverse group of customers. No individual end customer accounted for more than 10% of total revenue in fiscal period 1999, 2000 or 2001. No export sales to any given country accounted for more than 10% of total revenue in fiscal period 1999, 2000 or 2001.

 

Backlog

 

                Our backlog of scheduled and released orders as of December 31, 2001 was approximately $25.8 million as compared to approximately $85.9 million as of December 31, 2000.  This backlog consists of direct customer and distributor orders scheduled for delivery within the next 90 days.  Distributor orders accounted for the majority of the backlog in both periods.  Direct customer orders may be changed, rescheduled or cancelled under certain circumstances without penalty prior to shipment.  Additionally, distributor orders generally may be changed, rescheduled or cancelled without penalty prior to shipment.  Furthermore, distributor shipments are subject to rights of return and price adjustment.  Revenue associated with distributor shipments is not recognized until the product is resold to an end customer.  Typically, the majority of our revenue results from orders placed and filled within the same period.  Such orders are referred to as “turns orders.”  By definition, turns orders are not captured in a backlog measurement made at the beginning of a period.  We do not anticipate a significant change in this business pattern.  For all these reasons, backlog as of any particular date should not be used as a predictor of revenue for any future period.

 

Competition

 

                The semiconductor industry is intensely competitive and characterized by rapid rates of technological change, product obsolescence and price erosion.  Our current and potential competitors include a broad range of semiconductor companies from emerging companies to large, established companies, many of which have greater financial, technical, manufacturing, marketing and sales resources.

 

                The principal competitive factors in the PLD market include product features, price, customer support, and sales, marketing and distribution strength.  The availability of competitive software development tools is also critical.  In addition to product features such as density, speed, power consumption, reprogrammability, design flexibility and reliability, competition in the PLD market occurs on the basis of price and market acceptance of specific products and technology.  We believe that we compete favorably with respect to each of these factors.  We intend to continue to address these competitive factors by working to continually introduce product enhancements and new products, by seeking to establish our products as industry standards in their respective markets, and by working to reduce the manufacturing cost of our products.

 

                In the PLD market, we directly compete primarily with Actel, Altera and Xilinx, all of whom offer competing products.  We also indirectly compete with other PLD suppliers as well as other semiconductor companies who provide non-PLD based logic solutions.  Although to date we have not experienced significant competition from companies located outside the United States, such companies may become a more significant competitive factor in the future.  Competition may also increase as PLD companies seek to expand our markets.  Any such increases in competition could have a material adverse effect on our operating results.

 

Patents

 

                We seek to protect our products and wafer fabrication process technologies primarily through patents, trade secrecy measures, copyrights, mask work protection, trademark registrations, licensing restrictions, confidentiality agreements and other approaches designed to protect proprietary information.  There can be no assurance that others may not independently develop competitive technology not covered by our intellectual property rights or that measures we take to protect our technology will be effective.

 

                We hold numerous domestic, European and Asian patents and have patent applications pending in the United States,

 

7

 

Asia and Europe.  There can be no assurance that pending patent applications or other applications that may be filed will result in issued patents, or that any issued patents will survive challenges to their validity.  Although we believe that our patents have value, there can be no assurance that our patents, or any additional patents that may be issued in the future, will provide meaningful protection from competition.  We believe that our success will depend primarily upon the technical expertise, experience, creativity and the sales and marketing abilities of our personnel.

 

                Patent and other proprietary rights infringement claims are common in our industry.  There can be no assurance that, with respect to any claim made against us, we could obtain a license on terms or under conditions that would not harm our business.

 

Licenses and Agreements

 

Seiko Epson/Epson Electronics America

 

                Epson Electronics America (“EEA”), an affiliated U.S. distributor of Seiko Epson, has agreed to provide us with manufactured wafers in quantities based on six-month rolling forecasts.  We have committed to buy certain minimum quantities of wafers per month.  Wafers for our products are manufactured in Japan at Seiko Epson’s wafer fabrication facilities and are delivered to us by Epson Electronics America.  Prices for the wafers obtained from Epson Electronics America are reviewed and adjusted periodically.

 

                In 1997, and as subsequently amended in January 2002, we entered into an advance production payment agreement with Seiko Epson and EEA under which we agreed to advance approximately $69 million, payable upon completion of specific milestones, to Seiko Epson to finance construction of an eight-inch sub-micron semiconductor wafer manufacturing facility.  The timing of the payments is related to certain milestones in the development of the facility.  Under the terms of the agreement, the advance is to be repaid with semiconductor wafers over a multi-year period.  The agreement calls for wafers to be supplied by Seiko Epson through EEA pursuant to purchase agreements concluded with EEA.  Payments of approximately $51.2 million have been made under this agreement.

 

UMC Group

 

                Beginning in 1995, we entered into a series of agreements with UMC pursuant to which we agreed to make several equity investments in entities now directly owned by UMC.  Under the terms of these agreements, we invested approximately $68.5 million for the right to purchase a percentage of UMC’s wafer production at market prices.

 

                We currently own approximately 84 million shares of UMC common stock.  We will retain the right to purchase a certain percentage of UMC’s wafer production as long as we retain a certain percentage of these shares.

 

Chartered Semiconductor

 

                In 2002, in order to support our acquired FPGA products, Chartered Semiconductor and its affiliates agreed to provide us with manufactured wafers in quantities based on six-month rolling forecasts.  Wafers for our products are manufactured at the facilities of Chartered and its affiliates in Singapore.  We have committed to buy certain minimum quantities of wafers per month.

 

Advanced Micro Devices

 

                In 1999, as part of our acquisition of Vantis, we entered into an agreement with AMD pursuant to which we have cross–licensed Vantis patents with AMD patents, having an effective filing date on or before June 15, 1999, related to PLD products. This cross–license was made on a worldwide, non-exclusive and royalty-free basis.

 

8

 

                As part of our acquisition of Vantis Corporation, we acquired certain third–party license rights held by Vantis prior to the acquisition.  Included are rights to use certain Xilinx patents to manufacture, market and sell products.

 

Agere Systems

 

                In January 2002, as part of our acquisition of the FPGA business of Agere, we entered into a series of agreements with Agere to support the continuing operations of this business.  Pursuant to these agreements, for a limited period of time, Agere is providing us with certain manufacturing, engineering and transition services and sub-leased office space.

 

                We also entered into an intellectual property agreement with Agere and Agere Systems Guardian Corporation.  Pursuant to this agreement, these Agere companies assigned or licensed to us certain FPGA and FPSC patents, trademarks, software and other intellectual property rights and technology, and we licensed back rights in these same assets.  These cross–licenses were made on a worldwide and royalty-free basis.

 

Altera

 

                In July 2001, we entered into a comprehensive, royalty-free patent cross-license agreement and a multi-year patent peace agreement.

 

Employees

 

                As of December 31, 2001 we had 1,004 full-time employees.  We believe that our future success will depend, in part, on our ability to continue to attract and retain highly skilled technical and management personnel. None of our employees is subject to a collective bargaining agreement.  We have never experienced a work stoppage and consider our employee relations good.

 

Item 2. Properties.

 

                Our corporate headquarters consists of land and 200,000 square feet of buildings we own in Hillsboro, Oregon.  We also own a 13,000 square foot research and development facility and approximately 6,000 square feet of dormitory facilities in Shanghai, China.  We lease (through 2008) a 133,000 square foot research and development facility in San Jose, California.  We also lease, on a short-term basis, research and development facilities in Colorado, Illinois, Pennsylvania, Texas, Utah and the United Kingdom.  We also lease, on a short-term basis, office facilities in multiple metropolitan locations, for our domestic and international sales staff. Additionally, we lease (through 2006) an 80,000 square foot facility in Sunnyvale, California which has been subleased to a third party through the end of the lease term.

 

Item 3.    Legal Proceedings.

 

We are not currently a party to any material legal proceedings.

 

Item 4.  Submission of Matters to a Vote of Security Holders.

 

Not applicable.

 

9

 

Item 4(a).  Executive Officers of the Registrant.

 

 

MANAGEMENT

 

                The following individuals currently serve as our executive officers and directors:

 

Name		Age		Position
Cyrus Y. Tsui		56		Chief Executive Officer and Chairman of the Board
Steven A. Laub		43		President and Director
Stephen A. Skaggs		39		Senior Vice President, Chief Financial Officer and Secretary
Frank J. Barone		62		Corporate Vice President, Product Operations
Stephen M. Donovan		50		Corporate Vice President, Sales
Jonathan K. Yu		61		Corporate Vice President, Business Development
Martin R. Baker		46		Vice President and General Counsel
Randy D. Baker		43		Vice President and General Manager, Lattice Oregon
Albert L. Chan		52		Vice President and General Manager, Lattice Silicon Valley
Jan Johannessen		46		Vice President, Investments
Thomas J. Kingzett		55		Vice President, Reliability and Quality Assurance
Stanley J. Kopec		51		Vice President, Corporate Marketing
Andrew D. Robin		49		Vice President, New Venture Business
Rodney F. Sloss		58		Vice President, Finance
Kenneth K. Yu		54		Vice President and Managing Director, Lattice Asia
Mark O. Hatfield		79		Director
Daniel S. Hauer		65		Director
Soo Boon Koh		51		Director
Harry A. Merlo		76		Director
Larry W. Sonsini		60		Director

 

                Cyrus Y. Tsui joined Lattice in September 1988 as President, Chief Executive Officer and Director, and in March 1991 was named Chairman of the Board.  From 1987 until he joined, Mr. Tsui was Corporate Vice President and General Manager of the Programmable Logic Division of AMD.  He was Vice President and General Manager of the Commercial Products Divisions of Monolithic Memories Incorporated (MMI) from 1983 until its merger with AMD in 1987.  Mr. Tsui has held technical and managerial positions in the semiconductor industry for over 30 years and worked in the programmable logic industry since its inception.

 

                Steven A. Laub joined Lattice in June 1990 as Vice President and General Manager.  He was elected Senior Vice President and Chief Operating Officer in August 1996.  In October 2001, he was promoted to President and elected to our Board of Directors.

 

                Stephen A. Skaggs joined Lattice in December 1992 as Director, Corporate Development. He was elected Senior Vice President, Chief Financial Officer and Secretary in August 1996.

 

                Frank J. Barone joined Lattice in June 1999 as a Corporate Vice President as a result of our Vantis acquisition.  From September 1997 until he joined, Mr. Barone was Chief Operating Officer of Vantis.  Prior thereto, Mr. Barone held various technical and managerial positions at AMD.  He has worked in the programmable logic industry since 1978.

 

10

 

                Stephen M. Donovan joined Lattice in October 1989 and has served as Director of Marketing and Director of International Sales.  He was elected Vice President, International Sales in August 1993.  He was promoted to Corporate Vice President, Sales, in May 1998. Mr. Donovan has worked in the programmable logic industry since 1982.

 

                Jonathan K. Yu joined Lattice in February 1992 as Vice President, Operations. He was elected Corporate Vice President, Business Development in August 1996.  Mr. Yu has held technical and managerial positions in the semiconductor industry for over 30 years.

 

                Martin R. Baker joined Lattice in January 1997 as Vice President and General Counsel. From 1991 until he joined Lattice, Mr. Baker held legal positions with Altera Corporation.

 

                Randy D. Baker joined Lattice in April 1985 as Manager, Manufacturing and was promoted in 1988 to Director, Manufacturing.  He was elected Vice President, Manufacturing in August 1996.  In August 2001, he was promoted to Vice President and General Manager, Lattice Oregon.

 

                Albert L. Chan joined Lattice in May 1989 as California Design Center Manager and was promoted in 1991 to Director, California Product Development Center.  He was elected Vice President, California Product Development in August 1993.  He was promoted to Vice President and General Manager, Lattice Silicon Valley, in August 1997. Mr. Chan has worked in the programmable logic industry since 1983.

 

                Jan Johannessen rejoined Lattice in October 2001 as Vice President, Investments. Since 1993 he worked as an independent venture capitalist.  He originally joined Lattice in 1983 and served as Vice President and Chief Financial Officer between 1987 and 1993.

 

                Thomas J. Kingzett joined Lattice in July 1992 as Director, Reliability and Quality Assurance. He was elected Vice President, Reliability and Quality Assurance in May 1998. Mr. Kingzett has worked in the semiconductor industry for over 30 years.

 

                Stanley J. Kopec joined Lattice in August 1992 as Director, Marketing. He was elected Vice President, Corporate Marketing in May 1998.  Mr. Kopec has worked in the programmable logic industry since 1985.

 

                Andrew D. Robin joined Lattice in June 1999 as Vice President, New Venture Business as a result of the Vantis acquisition.  From March 1998 until he joined, Mr. Robin was Vice President, Marketing at Vantis.  Prior thereto, Mr. Robin held various marketing and managerial positions at AMD and MMI. Mr. Robin has worked in the programmable logic industry since 1984.

 

                Rodney F. Sloss joined Lattice in May 1994 as Vice President, Finance.

 

                Kenneth K. Yu joined Lattice in January 1991 as Director of Process Technology.  He has served as Managing Director, Lattice Asia since November 1992 and was elected Vice President, Lattice Asia in August 1993. Mr. Yu has held technical and managerial positions in the semiconductor industry for over 25 years.

 

                Mark O. Hatfield has been a member of our board of directors since 1997. Mr. Hatfield is a former U.S. Senator from Oregon.

 

                Daniel S. Hauer has been a member of our board of directors since 1987. Mr. Hauer is the former Chairman and Chief Executive Officer of Epson Electronics America.

 

11

 

                Soo Boon Koh joined our board of directors in August 2000. Ms. Koh is a general partner of iGlobe Ventures, a venture capital firm located in Singapore and the United States.

 

                Harry A. Merlo was a founding member of our board of directors in 1983.  Mr. Merlo is the President of Merlo Corporation and is the former founding President and Chairman of Louisiana–Pacific Corporation.

 

                Larry W. Sonsini has been a member of our board of directors since 1991.  Mr. Sonsini is Chairman of the Executive Committee of Wilson Sonsini Goodrich & Rosati, Professional Corporation, a law firm based in Palo Alto, California.

 

PART II

 

Item 5.  Market for the Registrant’s Common Stock and Related Stockholder Matters.

 

Our common stock is traded on the over-the-counter market and prices are quoted on the Nasdaq National Market under the symbol “LSCC.”  The following table sets forth the low and high sale prices for our common stock for the last two fiscal years and for the period since December 31, 2001.  On March 15, 2002, the last reported sale price of our common stock was $19.07.  As of March 15, 2002, we had approximately 460 stockholders of record.

 

	Low			High
2000:
First Quarter	$	20.44		$	41.31
Second Quarter	22.78			41.69
Third Quarter	23.00			40.00
Fourth Quarter	15.00			29.63
2001:
First Quarter	$	16.76		$	27.25
Second Quarter	15.88			27.65
Third Quarter	14.04			25.85
Fourth Quarter	14.36			22.65
2002:
First Quarter (through March 15, 2002)	$	17.06		$	24.14

 

All share amounts have been adjusted retroactively to reflect our two-for-one stock split effected in the form of  stock dividends of one share of common stock for each share of our outstanding common stock paid October 11, 2000.

 

The payment of dividends on our common stock is within the discretion of our Board of Directors.  We intend to retain earnings to finance the growth of our business.  We have not paid cash dividends and our Board of Directors does not expect to declare a cash dividend in the near future.

 

Item 6.  Selected Financial Data.

 

The section entitled “Selected Financial Data” in our 2001 Annual Report to Stockholders at page 19 is incorporated herein by reference.

 

12

 

Item 7.   Management’s Discussion and Analysis of Financial Condition and Results of Operations.

 

This report contains forward-looking statements within the meaning of Section 27A of the Securities Act of 1933, as amended, and Section 21E of the Securities Exchange Act of 1934, as amended. Actual results could differ materially from those projected in the forward-looking statements as a result of the factors set forth in the section entitled “Factors Affecting Future Results” and elsewhere in the report.

 

                Lattice Semiconductor Corporation designs, develops and markets high performance programmable logic devices, or PLDs, and related software. Programmable logic devices are widely-used semiconductor components that can be configured by the end customer as specific logic circuits, and enable the end customer to shorten design cycle times and reduce development costs.  Our end customers are primarily original equipment manufacturers in the communications, computing, industrial, military and consumer end markets.

 

                The 2001 and 2000 fiscal years are twelve-month periods, as compared to our nine-month fiscal period 1999.

 

Results of Operations

 

                The following table sets forth, for the periods indicated, the percentage of revenue represented by selected items reflected in our Consolidated Statement of Operations:

 

13

 

 

 

Acquisition of Vantis  As discussed in more detail in note 4 to our Consolidated Financial Statements, we completed the acquisition of Vantis Corporation (“Vantis”) from Advanced Micro Devices, Inc. (“AMD”) on June 15, 1999.  We paid approximately $500.1 million in cash for all of the outstanding capital stock of Vantis, plus $10.8 million in direct acquisition costs, $5.4 million of accrued pre-acquistion contingencies, $8.3 million of accrued  exit costs, and assumed certain liabilities of $34.5 million related to the Vantis business. In addition, we exchanged Lattice stock options for all of the outstanding stock options under the former Vantis employee stock plans with a calculated Black-Scholes value of $24.0 million. The total purchase price for Vantis was $583.1 million. The purchase price was allocated to the estimated fair value of assets acquired and liabilities assumed based on an independent appraisal and management estimates.  In-process research & development (IPR&D) costs were appraised at $89.0 million and charged to operations

 

14

 

on the acquisition date.  Remaining intangible asset costs are being amortized to operations over five years using the straight-line method (see New Accounting Pronouncements in note 1 to our Consolidated Financial Statements).

 

                The purchase was financed using a combination of cash reserves and a credit facility bearing interest at adjustable rates. The credit facility was replaced with Convertible Subordinated Notes in November 1999 (see note 8 to our Consolidated Financial Statements).

 

Revenue.   Revenue was $295.3 million in 2001, a decrease of 48% from 2000. Fiscal 2000 revenue of $567.8 million represented an increase of 111% from the $269.7 million recorded in fiscal period 1999. Revenue from the sale of high-density products represented 76%, 76% and 68% of total revenue for 2001, 2000 and fiscal period 1999, respectively.

 

                During 2001, the semiconductor and PLD markets experienced a significant downturn. Our revenue decrease in 2001 as compared to 2000, was a result of this downturn and the resultant decrease in demand for our products. Revenue declined across all geographies while the communications end market was particularly weak.

 

                In addition to our acquisition of Vantis, the increase in revenue in 2000 was primarily attributable to increased sales of high density products, particularly our new low-voltage high density products, in all geographic regions. Additionally, 2000 was a twelve-month fiscal year, as opposed to our nine-month fiscal period 1999.

 

Our sales by geographic region were as follows:

 

 

                Revenue from export sales as a percentage of total revenue was approximately 54% for 2001, 57% for 2000 and 53% for fiscal period 1999.  We expect export sales to continue to represent a significant portion of revenue.

 

                The average selling price of our products was approximately flat in 2001 as compared to 2000, but increased in 2000 as compared to fiscal period 1999. The average selling price for our products decreased significantly in the second half of 2001 as a result of the significant downturn in the semiconductor and PLD markets. Other fluctuations in average selling price, including the overall increase in 2000, were due primarily to product mix changes and increased sales of high density products. Although selling prices of mature products generally decline over time, this decline is at times offset by higher selling prices of new products. Our ability to maintain or increase the level of our average selling price is dependent on the continued development, introduction and market acceptance of new products. See “Factors Affecting Future Results.”

 

Gross Margin.  Our gross margin was 62% for 2001, 62% for 2000 and 60% for fiscal period 1999. Continued reductions in our overall manufacturing costs and improvements in our product mix generally offset an increased proportion of fixed

 

15

 

manufacturing costs in 2001. Product mix in 2001 was favorably affected by a higher ratio of previously deferred income compared to income from direct customer sales. The gross margin improvement in 2000 was primarily due to reductions in our manufacturing costs and improvements in our product mix. Reductions in manufacturing costs resulted primarily from on-going yield improvements, migration of products to more advanced technologies and smaller die sizes.

 

Research and Development.  Research and development expense was $71.7 million for 2001, $77.1 million in 2000 and $45.9 million in fiscal period 1999. The decrease in 2001 when compared to 2000 was attributable to a decrease in discretionary spending which more than offset headcount increases. In addition to our acquisition of Vantis, spending increases in 2000 were due to increased headcount and associated expenses related to development of new products. Additionally, 2000 was a twelve-month fiscal year, as opposed to our nine-month fiscal period 1999. We believe that a continued commitment to research and development is essential in order to maintain product leadership in our existing product families and provide innovative new product offerings, and therefore we expect to continue to make significant future investments in research and development.

 

Selling, General and Administrative.  Selling, general and administrative expense was $53.0 million in 2001, $81.1 million in 2000 and $50.7 million in fiscal period 1999. The decrease in 2001 when compared to 2000 was primarily due to lower variable costs associated with reduced revenue and profitability, reductions in discretionary spending and, to a lesser extent, the reversal in the third quarter of 2001 of $2.8 million of reserves established in the Vantis acquisition related to the now-settled Altera litigation (see note 11 to our Consolidated Financial Statements). Increased expenses in 2000 were primarily due to increased variable costs associated with higher revenue levels and our Vantis acquisition. Additionally, 2000 was a twelve-month fiscal period, as opposed to the nine- month fiscal period 1999.

 

In-Process Research and Development.  In-process research and development costs of approximately $89.0 million were incurred on June 15, 1999 in connection with our acquisition of Vantis (see note 4 to our Consolidated Financial Statements).

 

Amortization of Intangible Assets.  Amortization of intangible assets acquired in the Vantis acquisition and the acquisition of Integrated Intellectual Property, Inc. (“I2P”) on March 16, 2001 was $84.3 million in 2001, $81.9 million in 2000 and $45.8 million for fiscal period 1999. The increase in amortization for 2001 as compared to 2000 was primarily due to the I2P acquisition. The increase in amortization for 2000 was primarily due to a full year of amortization in 2000 as opposed to the approximately 6.5 months included in fiscal period 1999. The estimated weighted average useful life of the intangible assets for current technology, assembled workforce, customer lists, trademarks, patents and residual goodwill, created as a result of the acquisition, is approximately five years.

 

(Loss) Gain on Foundry Investments. The gain on foundry investments recorded in the first quarter of 2000 and the loss on foundry investments recorded in the third quarter of 2001 represent equity market appreciation and subsequent impairment loss on our UMC common shares (see note 5 to our Consolidated Financial Statements).

 

Interest Income.  Interest income was $17.7 million in 2001, $16.2 million in 2000, and $6.1 million in fiscal period 1999. The increase in 2001 when compared to 2000 was attributable to overall increased cash balances generated from our follow-on stock offering, completed in July 2000, which more than offset lower interest rates on invested balances in 2001. The 2000 interest income increase was due to our follow-on stock offering, cash generated from operations and stock option exercises. Additionally, 2000 was a twelve-month fiscal period as opposed to our nine-month fiscal period 1999.

 

Interest Expense.  Interest expense was approximately $14.0 million in both 2001 and 2000 and $9.7 million in fiscal period 1999.  Substantially all interest expense resulted from the debt issued to partially fund our Vantis acquisition. The 2000 interest expense increase of 44% was due to the fact that acquisition-related debt was outstanding for all of 2000, but only for 6.5 months in fiscal period 1999.

 

16

 

(Benefit) Provision for Income Taxes. The benefit for income taxes for 2001 results in an effective tax rate of (37.0%), as compared to 35.9% in 2000 and (37.6%) for fiscal period 1999. The tax benefit in 2001 is the result of the pretax loss reported in the period. The rate associated with the tax benefit in 2001 is higher than the provision rate in 2000 because of the proportional impact of our marginal tax rate applied to the unrealized gain in 2000 and subsequent impairment loss in 2001 related to our foundry investments (see note 5 to our Consolidated Financial Statements) in comparison to taxes on operating income and non-taxable investment income. The benefit for income taxes for fiscal period 1999 was attributable to the tax effect of the in-process research and development cost recognized in conjunction with our Vantis acquisition. The effective rate for all periods presented is lower than the combined federal and state statutory rates primarily because of tax-exempt investment income and tax credits.

 

Extraordinary Item, Net of Income Taxes.  The extraordinary item, net of income taxes, in fiscal period 1999 represents the writeoff of unamortized loan fees related to the early retirement of our credit facility in connection with the re-financing of our acquisition of Vantis.

 

Factors Affecting Future Results

 

A downturn in the communications equipment or computing end markets will cause a reduction in demand for our products and limit our ability to maintain or increase our revenue and profit levels.

 

A significant portion of our revenue is derived from customers in the communications equipment and computing end markets.  A downturn in the overall global economy or in the economies of the countries where we derive significant revenue could lead to a contraction of capital spending on information technology.  This in turn could lead to a reduction in the demand for communications or computing equipment and for our products.

 

Due to a deterioration in overall economic conditions and a significant reduction in information technology capital spending, the communications and computing end markets declined in 2001 when compared to prior years.  In addition, the abrupt transition from an environment of rapid growth to the current environment in these end equipment markets has resulted in an excess of component inventory within our end customers.  At present and in the future when these or other similar conditions exist, there is likely to be an adverse effect on our operating results.

The cyclical nature of the semiconductor industry may limit our ability to maintain or increase revenue and profit levels during future industry downturns.

 

The semiconductor industry is highly cyclical, to a greater extent than other less dynamic or less technology-driven industries.  Our financial performance has periodically been negatively affected by past downturns in the semiconductor industry.  Factors that have contributed to these downturns include:

•                  the cyclical nature of the demand for the products of semiconductor customers;

•                  general reductions in inventory levels by customers;

•                  excess production capacity; and

•                  accelerated declines in average selling prices.

In 2001, the semiconductor industry experienced a significant downturn.  At present and in the future when these or other similar conditions exist, there is likely to be an adverse effect on our operating results.

 

17

 

We may experience unexpected difficulties integrating the FPGA business we recently purchased from Agere Systems.

 

On January 18, 2002, we acquired the field programmable gate array (“FPGA”) business of Agere Systems and are currently in the process of integrating this business with our operations.  If our integration is unsuccessful, more difficult or more time consuming than originally planned, we may incur unexpected disruptions to our ongoing business.  These disruptions could harm our operating results.  Further, the following specific factors may adversely affect our ability to integrate the FPGA business of Agere:

•                  we may experience unexpected losses of key employees or customers;

•                  we may not be able to coordinate our new product and process development in a way which permits us to bring
future new products to the market in a timely manner;

•                  we may experience unexpected costs and discover unexpected liabilities;

•                  we  may not achieve expected levels of revenue growth, cost reduction and profitability improvement; and

•                  we may experience difficulties or delays in conforming the standards, processes, procedures and controls of our two businesses.

 

In addition, as part of our acquisition, we entered into agreements with Agere Systems to obtain certain manufacturing, intellectual property and transition support and services.  In the event that Agere fails to provide this support and service, or provides such support and service at a level of quality and timeliness inconsistent with the historical delivery of such support and service, our ability to integrate the FPGA business will be hampered and our operating results may be harmed.

We may be unsuccessful in defining, developing or selling new products required to maintain or expand our business.

 

As a semiconductor company, we operate in a dynamic environment marked by rapid product obsolescence.  Our future success depends on our ability to introduce new or improved products that meet customer needs while achieving acceptable margins.  If we fail to introduce these new products in a timely manner or these products fail to achieve market acceptance, our operating results would be harmed.

 

The introduction of new products in a dynamic market environment presents significant business challenges.  Product development commitments and expenditures must be made well in advance of product sales.  The success of a new product depends on accurate forecasts of long-term market demand and future technology developments.

 

Our future revenue growth is dependent on market acceptance of our new product families and the continued market acceptance of our software development tools.  The success of these products is dependent on a variety of specific technical factors including:

•                  successful product definition;

•                  timely and efficient completion of product design;

•                  timely and efficient implementation of wafer manufacturing and assembly processes;

 

18

 

•                  product performance; and

•                  the quality and reliability of the product.

 

If, due to these or other factors, our new products do not achieve market acceptance, our operating results would be harmed.

Our products may not be competitive if we are unsuccessful in migrating our manufacturing processes to more advanced technologies or alternative fabrication facilities.

 

To develop new products and maintain the competitiveness of existing products, we need to migrate to more advanced wafer manufacturing processes that use larger wafer sizes and smaller device geometries.  We also may need to use additional foundries.  Because we depend upon foundries to provide their facilities and support for our process technology development, we may experience delays in the availability of advanced wafer manufacturing process technologies at existing or new wafer fabrication facilities.  As a result, volume production of our advanced process technologies at the new fabs of Seiko Epson, UMC or future foundries may not be achieved.  This could harm our operating results.

 

In late 2001, UMC informed us that as part of an overall capacity rationalization they are planning to close certain of their fabrication facilities.  We were developing an advanced wafer manufacturing process at one of the UMC fabs that has been closed.  With UMC’s support, we have transferred this process to alternative UMC fabs.  However, transfer of a manufacturing process is a technically demanding and time intensive challenge.  As a result, our new product introduction schedules have been delayed.  This could harm our operating results.

Our marketable securities, which we hold for strategic reasons, are subject to equity price risk and their value may fluctuate.

 

Currently we hold substantial equity in UMC Corporation, which we acquired as part of a strategic investment to obtain certain manufacturing rights.  The market price and valuation of these equity shares has fluctuated widely due to market and other conditions over which we have little control.  During the quarter ended September 30, 2001, we recorded a $152.8 million pre-tax impairment loss related to this investment.  In the future, UMC shares may continue to experience significant price volatility.  We have not attempted to reduce or eliminate this equity price risk through hedging or similar techniques and hence substantial, sustained changes in the market price of UMC shares could impact our financial results.  To the extent that the market value of our UMC shares experiences further deterioration for an extended period of time, our net income could be reduced.

Our future quarterly operating results may fluctuate and therefore may fail to meet expectations.

 

Our quarterly operating results have fluctuated and may continue to fluctuate.  Consequently, our operating results may fail to meet the expectations of analysts and investors.  As a result of industry conditions and the following specific factors, our quarterly operating results are more likely to fluctuate and are more difficult to predict than a typical non-technology company of our size and maturity:

•                  general economic conditions in the countries where we sell our products;

•                  conditions within the end markets into which we sell our products;

•                  the cyclical nature of demand for our customers’ products;

 

19

 

 

•                  excessive inventory accumulation by our end customers;

•                  the timing of our and our competitors’ new product introductions;

•                  product obsolescence;

•                  the scheduling, rescheduling and cancellation of large orders by our customers;

•                  our ability to develop new process technologies and achieve volume production at the new fabs of Seiko Epson, UMC or at other foundries;

•                  changes in manufacturing yields;

•                  adverse movements in exchange rates, interest rates or tax rates; and

•                  the availability of adequate supply commitments from our wafer foundries and assembly and test subcontractors.

 

As a result of these factors, our past financial results are not necessarily a good predictor of our future results.

Our stock price may continue to experience large short-term fluctuations.

 

In recent years, the price of our common stock has fluctuated greatly.  These price fluctuations have been rapid and severe and have left investors little time to react.  The price of our common stock may continue to fluctuate greatly in the future due to a variety of company specific factors, including:

•                  quarter-to-quarter variations in our operating results;

•                  shortfalls in revenue or earnings from levels expected by securities analysts; and

•                  announcements of technological innovations or new products by other companies.

Our wafer supply may be interrupted or reduced, which may result in a shortage of finished products available for sale.

 

We do not manufacture finished silicon wafers.  Currently, our silicon wafers are manufactured by Seiko Epson in Japan, UMC in Taiwan, Chartered Semiconductor in Singapore, Agere Systems and AMD in the United States.  If Seiko Epson, through its U.S. affiliate, Epson Electronics America, UMC or Chartered significantly interrupts or reduces our wafer supply, our operating results could be harmed.

 

In the past, we have experienced delays in obtaining wafers and in securing supply commitments from our foundries.  At present, we anticipate that our supply commitments are adequate.  However, these existing supply commitments may not be sufficient for us to satisfy customer demand in future periods.  Additionally, notwithstanding our supply commitments we may still have difficulty in obtaining wafer deliveries consistent with the supply commitments.  We negotiate wafer prices and supply commitments from our suppliers on at least an annual basis.  If any of Seiko Epson, Epson Electronics America, UMC or Chartered were to reduce its supply commitment or increase its wafer prices, and we cannot find alternative sources of wafer supply, our operating results could be harmed.

 

20

 

Many other factors that could disrupt our wafer supply are beyond our control.  Since worldwide manufacturing capacity for silicon wafers is limited and inelastic, we could be harmed by significant industry-wide increases in overall wafer demand or interruptions in wafer supply.  Additionally, a future disruption of Seiko Epson’s, UMC’s or Chartered’s foundry operations as a result of a fire, earthquake or other natural disaster could disrupt our wafer supply and could harm our operating results.

If our foundry partners experience quality or yield problems, we may face a shortage of finished products available for sale.

 

We depend on our foundries to deliver reliable silicon wafers with acceptable yields in a timely manner.  As is common in our industry, we have experienced wafer yield problems and delivery delays.  If our foundries are unable to produce silicon wafers that meet our specifications, with acceptable yields, for a prolonged period, our operating results could be harmed.

 

The majority of our revenue is derived from products based on a specialized silicon wafer manufacturing process technology called E²CMOS.  The reliable manufacture of high performance E²CMOS semiconductor wafers is a complicated and technically demanding process requiring:

•                  a high degree of technical skill;

•                  state-of-the-art equipment;

•                  the absence of defects in the masks used to print circuits on a wafer;

•                  the elimination of minute impurities and errors in each step of the fabrication process; and

•                  effective cooperation between the wafer supplier and the circuit designer.

 

As a result, our foundries may experience difficulties in achieving acceptable quality and yield levels when manufacturing our silicon wafers.

If our assembly and test subcontractors experience quality or yield problems, we may face a shortage of finished products available for sale.

 

We rely on subcontractors to assemble and test our devices with acceptable quality and yield levels.  As is common in our industry, we have experienced quality and yield problems in the past.  If we experience prolonged quality or yield problems in the future, our operating results could be harmed.

 

The majority of our revenue is derived from semiconductor devices assembled in advanced packages.  The assembly of advanced packages is a complex process requiring:

•                  a high degree of technical skill;

•                  state-of-the-art equipment;

•                  the absence of defects in lead frames used to attach semiconductor devices to the package;

•                  the elimination of raw material impurities and errors in each step of the process; and

 

21

 

•                  effective cooperation between the assembly subcontractor and the device manufacturer.

 

As a result, our subcontractors may experience difficulties in achieving acceptable quality and yield levels when assembling and testing our semiconductor devices.

Deterioration of conditions in Asia may disrupt our existing supply arrangements and result in a shortage of finished products available for sale.

 

All three of our major silicon wafer suppliers operate fabs located in Asia.  Our finished silicon wafers are assembled and tested by independent subcontractors located in China, Malaysia, the Philippines, Singapore, South Korea, Taiwan and Thailand.  A prolonged interruption in our supply from any of these subcontractors could harm our operating results.

 

Economic, financial, social and political conditions in Asia have historically been volatile.  Financial difficulties, governmental actions or restrictions, prolonged work stoppages or any other difficulties experienced by our suppliers may disrupt our supply and could harm our operating results.

 

Our wafer purchases from Seiko Epson are denominated in Japanese yen.  The value of the dollar with respect to the yen fluctuates.  Substantial deterioration of dollar-yen exchange rates could harm our operating results.

Export sales account for a substantial portion of our revenues and may decline in the future due to economic and governmental uncertainties.

 

Our export sales are affected by unique risks frequently associated with foreign economies including:

•                  changes in local economic conditions;

•                  exchange rate volatility;

•                  governmental controls and trade restrictions;

•                  export license requirements and restrictions on the export of technology;

•                  political instability or terrorism;

•                  changes in tax rates, tariffs or freight rates;

•                  interruptions in air transportation; and

•                  difficulties in staffing and managing foreign sales offices.

 

For example, our export sales have historically been affected by regional economic crises.  Significant changes in the economic climate in the foreign countries where we derive our export sales could harm our operating results.

 

22

 

We may not be able to successfully compete in the highly competitive semiconductor industry.

 

The semiconductor industry is intensely competitive and many of our direct and indirect competitors have substantially greater financial, technological, manufacturing, marketing and sales resources.  If we are unable to compete successfully in this environment, our future results will be adversely affected.

 

The current level of competition in the programmable logic market is high and may increase as our market expands.  We currently compete directly with companies that have licensed our products and technology or have developed similar products.  We also compete indirectly with numerous semiconductor companies that offer products and solutions based on alternative technologies.  These direct and indirect competitors are established multinational semiconductor companies as well as emerging companies.  We also may experience significant competition from foreign companies in the future.

We may fail to retain or attract the specialized technical and management personnel required to successfully operate our business.

 

To a greater degree than most non-technology companies or larger technology companies, our future success depends on our ability to attract and retain highly qualified technical and management personnel.  As a mid-sized company, we are particularly dependent on a relatively small group of key employees.  Competition for skilled technical and management employees is intense within our industry.  As a result, we may not be able to retain our existing key technical and management personnel.  In addition, we may not be able to attract additional qualified employees in the future.  If we are unable to retain existing key employees or are unable to hire new qualified employees, our operating results could be adversely affected.

If we are unable to adequately protect our intellectual property rights, our financial results and competitive position may suffer.

 

Our success depends in part on our proprietary technology.  However, we may fail to adequately protect this technology.  As a result, we may lose our competitive position or face significant expense to protect or enforce our intellectual property rights.

 

We intend to continue to protect our proprietary technology through patents, copyrights and trade secrets.  Despite this intention, we may not be successful in achieving adequate protection.  Claims allowed on any of our patents may not be sufficiently broad to protect our technology.  Patents issued to us also may be challenged, invalidated or circumvented.

 

Finally, our competitors may develop similar technology independently. Companies in the semiconductor industry vigorously pursue their intellectual property rights.  If we become involved in protracted intellectual property disputes or litigation we may utilize substantial financial and management resources, which could have an adverse effect on our operating results.

 

We may also be subject to future intellectual property claims or judgments.  If these were to occur, we may not be able to obtain a license on favorable terms or without our operating results being adversely affected.

 

Critical Accounting Policies

 

On December 12, 2001 and again on February 13, 2002 the Securities and Exchange Commission proposed new corporate

 

23

 

disclosure rules related to critical accounting policies.  Critical Accounting Policies are those “that are both most important to the portrayal of a company’s financial condition and results and require management’s most difficult, subjective and complex judgements, often as a result of the need to make estimates about the effect of matters that are inherently uncertain.” A description of our critical accounting policies follows.

 

Revenue recognition. Revenue from direct customers is recognized upon shipment provided that persuasive evidence of a sales arrangement exists, the price is fixed, title has transferred, collection of resulting receivables is probable, there are no customer acceptance requirements and no remaining significant obligations.  Certain of our sales are made to distributors under agreements providing price protection and right of return on unsold merchandise.  Revenue and costs relating to such distributor sales are deferred until the product is sold by the distributor and related revenue and costs are then reflected in income.

 

Deferred income. In determining the amount of deferred income related to sales to distributors, we make estimates regarding sales prices and margins to be earned by our distributors upon sales to our end customers.

 

Inventory and inventory valuation allowances. We value inventory at the lower of cost or market on a quarterly basis. In addition, we establish reserves for unproven, excess and obsolete inventories. To value our inventory, we make a number of estimates and assumptions including future price declines and forecasted demand for our products.

 

Accounting for income taxes. To report income tax expense related to operating results, we record current and deferred income tax assets and liabilities in our balance sheet. In determining the value of our deferred tax assets, we make estimates of future taxable income. We believe that it is more likely than not that we will earn sufficient future taxable income to realize these deferred tax assets, and therefore, we do not provide for valuation allowances on our deferred tax assets.

 

New Accounting Pronouncements

 

                In June 1998, the FASB issued SFAS 133, “Accounting for Derivatives Instruments and Hedging Activities.” SFAS 133 establishes new accounting treatment for derivatives and hedging activities and supersedes and amends a number of existing accounting standards.  We adopted this pronouncement in the first quarter of 2001; such adoption did not and has not had a material effect on the consolidated financial statements.

 

In June 2001, the FASB issued SFAS 142, “Goodwill and Other Intangible Assets,” which supersedes APB Opinion No. 17, “Intangible Assets.” SFAS 142, among other things, establishes new standards for intangible assets acquired in a business combination, eliminates amortization of goodwill and sets forth requirements to periodically evaluate goodwill for impairment. We will adopt this statement during the first quarter of 2002, at which time goodwill and certain intangibles with indefinite lives will no longer be amortized, eliminating approximately $8 million of existing quarterly amortization. Amortization expense for the fourth quarter of 2001 and for the year ended December 31, 2001 was approximately $21.3 and $84.3 million, respectively. As of December 31, 2001, the consolidated balance sheet caption “Intangible Assets” included approximately $81.4 million of goodwill and $125.1 million of net other intangible assets. We will complete an initial goodwill impairment assessment in 2002 to determine if a transition impairment charge should be recognized under SFAS 142. We do not anticipate a material impairment charge upon the completion of the initial impairment review.

 

In October 2001, the FASB issued SFAS 144, “Accounting for the Disposal of Long-Lived Assets,” which supersedes SFAS 121, “Accounting for the Impairment of Long-Lived Assets and for Long-Lived Assets to be Disposed Of.” SFAS 144 retains the fundamental provisions of SFAS 121 regarding the recognition and measurement of the impairment of long-lived assets to be held and used and the measurement of long-lived assets to be disposed by sale, but provides additional definition and measurement criteria for determining when an impairment has occurred. Goodwill and financial

 

24

assets are excluded from the scope of SFAS 144, however amortizable intangible assets fall within its scope. We do not expect this pronouncement to materially affect our financial statements when we adopt it during the first quarter of 2002.

 

Item 7(a) Quantitative and Qualitative Disclosures About Market Risk

 

As of December 31, 2001 and December 31, 2000 our investment portfolio consisted of fixed income securities of $508.2 million and $507.3 million, respectively. As with all fixed income instruments, these securities are subject to interest rate risk and will decline in value if market interest rates increase. If market rates were to increase immediately and uniformly by 10% from levels as of December 31, 2001 and December 31, 2000 the decline in the fair value of our portfolio would not be material. Further, we have the ability to hold our fixed income investments until maturity and, therefore, we would not expect to recognize such an adverse impact in our income or cash flows.

 

We have international subsidiary and branch operations. Additionally, a portion of our silicon wafer purchases are denominated in Japanese yen. We therefore are subject to foreign currency rate exposure. To mitigate rate exposure with respect to our yen-denominated wafer purchases, we maintain yen-denominated bank accounts and bill our Japanese customers in yen. The yen bank deposits are utilized to hedge specific and firm yen-denominated wafer purchases. If the foreign currency rates were to fluctuate by 10% from rates at December 31, 2001 and December 31, 2000, the effect on our consolidated financial statements would not be material. However, there can be no assurance that there will not be a material impact in the future.

 

We are exposed to equity price risk due to our equity investment in UMC (see note 5 to our Consolidated Financial Statements). Neither a 10% increase nor a further 10% decrease in equity price related to this investment would have a material effect on our consolidated financial statements. We have not attempted to reduce or eliminate this equity price risk through hedging or similar techniques and hence substantial, sustained changes in the market price of UMC shares could impact our financial results.  To the extent that the market value of our UMC shares experiences further deterioration for an extended period of time, our net income could be reduced.

 

Liquidity and Capital Resources

 

                As of December 31, 2001, our principal source of liquidity was $531.6 million of cash and short-term investments, a slight decrease from the balance of $535.4 million at December 31, 2000. Working capital increased to $617.2 million at December 31, 2001 from $552.2 million at December 31, 2000. This increase was primarily due to decreases in deferred income, accounts payable and accrued expenses, which more than offset a decrease in our accounts receivable. These decreases were associated with the significant downturn in the semiconductor and PLD markets during 2001 and our lower revenue and operating expense levels. During 2001, we generated approximately $7.0 million of cash and cash equivalents from our operations compared with $114.3 million during 2000. This reduction in cash generation was driven primarily by reduced receipts from end customers and distributors in conjunction with lower revenue levels and reduced cash inflow from stock option exercises.

 

                Accounts receivable at December 31, 2001 decreased by $30.2 million, or 61%, as compared to the balance at December 31, 2000. This decrease was primarily due to decreased billings and revenue levels during the year. Inventories increased by $5.4 million, or nine percent, as compared to the balance at December 31, 2000 primarily due to lower revenue levels and the continued receipt of wafers started in the last half of 2000. Wafer starts were significantly reduced throughout 2001 and inventory levels stabilized in the second half of 2001. Prepaid expenses and other current assets increased by approximately $5.5 million, or 24%, as compared to the balance at December 31, 2000. This increase is due primarily to estimated income taxes paid in the first quarter of 2001 which are now refundable as a result of the pre-tax loss recorded in the second through fourth quarters of 2001. Current deferred tax assets decreased by approximately $17.5 million, or 36%, as compared to the balance at December 31, 2000. This was primarily due to the decrease in deferred income on sales to distributors (which is recognized currently for income tax purposes), and to a lesser extent the timing of

 

25

 

deductions for certain expenses and allowances. Foundry investments, advances and other assets decreased by approximately $27.0 million, or 14% as compared to the balance at December 31, 2000. This decrease was primarily due to market value depreciation of our investment in UMC (see note 5 to our Consolidated Financial Statements). Net intangible assets decreased by $79.9 million, or 28% as compared to the balance at December 31, 2000, primarily due to amortization of goodwill and other intangibles, partially offset by new intangible assets acquired during the period which are being amortized over four years. Amortization expense for these new assets totaled approximately $1.4 million, including $0.4 million of deferred compensation expense. The increase in non-current deferred income taxes of $31.0 million, or 89%, at December 31, 2001 as compared to December 31, 2000 is due primarily to a reduction of the deferred tax liability originally recorded on January 3, 2000 in conjunction with the gain recognized on the appreciation of our UMC shares (see note 7 to our Consolidated Financial Statements). The balance of this deferred tax liability of $27.9 million at December 31, 2000, was netted against non-current deferred income tax assets in our consolidated balance sheet. This liability was eliminated in the third quarter of 2001 as our impairment loss recognized in the third quarter of 2001 on the UMC shares was slightly in excess of the original gain recorded. In conjunction with the subsequent market appreciation of the UMC shares in the fourth quarter of 2001, a deferred tax liability of $13.3 million was recorded. The increase in non-current deferred taxes is also due, to a lesser extent, to the net tax effect of intangible asset amortization.

 

                 Accounts payable and accrued expenses at December 31, 2001 decreased by $54.0 million, or 73%, as compared to the balance at December 31, 2000. This decrease is due primarily to decreased wafer purchases and contracted assembly activities in response to decreased customer demand and revenue levels. The $6.7 million, or 71% decrease in income taxes payable at December 31, 2001 as compared to the balance at December 31, 2000 is primarily attributable to the net loss recorded in 2001 and to the timing of tax deductions and payments. Deferred income at December 31, 2001 decreased by $40.1 million, or 69%, as compared to the balance at December 31, 2000, due primarily to decreased billings to distributors associated with decreased shipments and lower revenue levels.

 

                On October 28, 1999, we issued $260 million in 4 ¾ % convertible subordinated notes due on November 1, 2006. These notes require that we pay interest semi-annually on May 1 and November 1. Holders of these notes may convert them into shares of our common stock at any time on or before November 1, 2006, at a conversion price of $20.72 per share, subject to adjustment in certain events. Beginning on November 6, 2002 and ending on October 31, 2003, we may redeem the notes in whole or in part at a redemption price of 102.71% of the principal amount. In the subsequent three twelve-month periods, the redemption price declines to 102.04%, 101.36% and 100.68% of principal, respectively. The notes are subordinated in right of payment to all of our senior indebtedness, and are subordinated to all liabilities of our subsidiaries. At December 31, 2001, we had no senior indebtedness and our subsidiaries had $2.5 million of other liabilities. Issuance costs relative to the convertible subordinated notes are included in Other Assets and aggregated approximately $6.9 million and are being amortized to expense over the life of the notes. Accumulated amortization amounted to approximately $3.6 million at December 31, 2001.

 

                On June 15, 1999, we entered into a credit agreement with a group of lenders and ABN AMRO Bank N.V. as administrative agent for the lender group.  The credit agreement consisted of two credit facilities: a $60 million unsecured revolving credit facility (“Revolver”), and a $220 million unsecured reducing term loan (“Term Loan”), both expiring and due on June 30, 2002.  On June 15, 1999, we borrowed $220 million under the Term Loan and approximately $33 million under the Revolver. The $33 million Revolver was repaid in full during the third calendar quarter of 1999. In conjunction with the issuance of the convertible subordinated notes, we repaid the $220 million Term Loan in full during the fourth calendar quarter of fiscal 1999. Remaining unamortized loan fees at the time of repayment, aggregating approximately $2.6 million ($1.665 million net of income taxes or a charge of $0.02 for basic and diluted earnings per share), were written off and are reflected in our Consolidated Statement of Operations as an Extraordinary Item, Net of Income Taxes.

 

                We do not have any financial partnerships with unconsolidated entities, such as entities often referred to as structured finance or special purpose entities, which are often established for the purpose of facilitating off-balance sheet

 

26

 

arrangements or other contractually narrow or limited purposes. Accordingly, we are not exposed to any financing, liquidity, market or credit risk that could arise if we had such relationships.

 

                Capital expenditures were approximately $13.8 million, $25.9 million and $15.7 million for 2001, 2000 and fiscal period 1999, respectively. We expect to spend approximately $15 million to $20 million for the fiscal year ending December 31, 2002.

 

Certain of our facilities and equipment are leased under operating leases, which expire at various times through 2008.  Rental expense under the operating leases was approximately $5.1 million, $5.5 million and $2.8 million for 2001, 2000, and fiscal period 1999, respectively. Future minimum lease commitments at December 31, 2001 are as follows (in thousands):

 

Year
2002		$	7,418
2003		6,903
2004		6,509
2005		5,903
2006		4,628
Later years		8,111
		$	39,472

 

                Included in these amounts are certain properties which are currently subleased. A portion of this sublease income is payable to the property owner.  Future minimum sublease receipts, based on agreements in place at December 31, 2001, net of such payments are as follows (in thousands):

 

Year
2002		$	2,623
2003		2,473
2004		2,555
2005		2,622
2006		886
		$	11,159

 

We currently own approximately 84 million shares of UMC common stock. Restrictions by UMC and the Taiwan government apply to approximately 28% of these shares. If we liquidate our UMC shares, it is likely that the amount of any future realized gain or loss will be different from the accounting gain or loss reported in prior periods.

 

                In December 2000, our Board of Directors authorized management to repurchase up to five million shares of our common stock. As of December 31, 2001, we had repurchased 1,136,000 shares (596,000 in 2001) at an aggregate cost of approximately $20.0 million ($10.6 million in 2001).

 

 

 

                In March 1997 and as subsequently amended in January 2002, we entered into an advance payment production agreement with Seiko Epson and Epson Electronics America, Inc.  (“EEA”) under which we agreed to advance approximately $69 million, payable upon completion of specific milestones, to Seiko Epson to finance construction of an eight-inch sub-micron semiconductor wafer manufacturing facility.  Under the terms of the agreement, the advance is to be repaid with semiconductor wafers over a multi-year period.  No interest income is recorded.  The agreement calls for wafers

 

27

 

to be supplied by Seiko Epson through EEA pursuant to purchase agreements with EEA. Payments of approximately $51.2 million have been made under this agreement. Approximately $3.4 million of these advances are expected to be repaid with semiconductor wafers during fiscal year 2002 and are thus reflected as part of “Prepaid expenses and other current assets” in our Consolidated Balance Sheet.

 

                On December 10, 2001, we announced a definitive agreement to acquire the FPGA business of Agere Systems, Inc. for $250 million in cash. This acquisition was completed on January 18, 2002 and financed with cash on hand. The transaction will be accounted for as a purchase.

 

                The acquisition includes a general purpose ORCA^Ò FPGA product portfolio, a field programmable system chip (FPSC) product portfolio and all related software design tools. In addition, we also acquired certain intellectual property cores and patents unique to Agere’s FPGA business and entered into a cross-license agreement with Agere covering certain FPGA and FPSC patents, intellectual property and technology. As part of the transaction, we also hired approximately 100 Agere product development, marketing and technical sales employees.

 

                The $250 million purchase price, associated costs and assumed liabilities are tax deductible (over 15 years for substantially all of the sum).  Management, with the assistance of a third party valuation of intangible assets, attributed $65 million to purchased technology, $24 million to in-process research and development costs, and $24 million to a non-compete agreement and to licensed technology.  Value attributed to acquired tangible assets and assumed liabilities is not material to our financial statements.  Goodwill is the difference between a) the sum of the purchase price, associated costs and assumed liabilities, and b) the fair value of acquired assets.  Purchased and licensed (non-goodwill) intangible assets will be amortized over approximately 7 years on a straight line basis except in-process research and development costs which will be charged to operations in the March 2002 quarter.

 

                We believe that our existing liquid resources, expected cash generated from operations and existing credit facilities combined with our ability to borrow additional funds will be adequate to meet our operating and capital requirements and obligations for the next 12 months, including our recent acquisition of the Agere FPGA business.

 

                We may in the future seek new or additional sources of funding. In addition, in order to secure additional wafer supply, we may from time to time consider various financial arrangements including joint ventures, equity investments, advance purchase payments, loans, or similar arrangements with independent wafer manufacturers in exchange for committed wafer capacity. To the extent that we pursue any such additional financing arrangements, additional debt or equity financing may be required. There can be no assurance that such additional financing will be available when needed or, if available, will be on favorable terms. Any future equity financing will decrease existing stockholders’ equity percentage ownership and may, depending on the price at which the equity is sold, result in dilution.

 

Item 8.  Financial Statements and Supplementary Data.

 

The section entitled “Consolidated Financial Statements” on pages 20 through 32 in our 2001 Annual Report to Stockholders is incorporated herein by reference.

 

 

 

 

Consolidated Financial Statement Schedules:
Report of Independent Accountants on Financial Statement Schedule			S-1
Schedule II- Valuation and Qualifying Accounts			S-2

 

28

 

Item 9.  Changes in and Disagreements with Accountants On Accounting and Financial Disclosure.

 

Not applicable.

 

With the exception of the information expressly incorporated by reference from the Annual Report to Stockholders into Parts II and IV of this Form 10-K, the Company’s Annual Report to Stockholders is not to be deemed filed as part of this Report.

 

PART III

 

Certain information required by Part III is omitted from this Report in that the Company will file its definitive proxy statement for the Annual Meeting of Stockholders to be held on May 7, 2002, pursuant to Regulation 14A of the Securities Exchange Act of 1934 (the “Proxy Statement”), not later than 120 days after the end of the fiscal year covered by this Report, and certain information included in the Proxy Statement is incorporated herein by reference. With the exception of the information expressly incorporated by reference from the Proxy Statement, the Company’s Proxy Statement is not to be deemed filed as a part of this report.

 

Item 10.  Directors and Executive Officers of the Registrant.

 

The caption entitled “Proposal 1: Election of Directors” in the Company’s Proxy Statement is incorporated herein by reference.  Information with respect to executive officers of the Company is included under Item 4(a) of Part I of this Report and is incorporated herein by reference.

 

Item 11.  Executive Compensation.

 

The caption entitled “Proposal 1: Election of Directors,” “Executive Compensation” “Options Granted and Options Exercised in the Last Fiscal Year” and “Comparison of Total Cumulative Stockholder Return” in the Company’s Proxy Statement is incorporated herein by reference.

 

 

Item 12.  Security Ownership of Certain Beneficial Owners and Management.

 

The caption entitled “Security Ownership of Certain Beneficial Owners and Management” in the Company’s Proxy Statement is incorporated herein by reference.

 

Item 13.  Certain Relationships and Related Transactions.

 

The caption entitled “Proposal 1: Election of Directors - Transactions with Management” in the Company’s Proxy Statement is incorporated herein by reference.

 

PART IV

 

Item 14. Exhibits, Financial Statement Schedules and Reports on Form 8-K.

 

            (a)(1) and (2) Financial Statements and Financial Statement Schedules.

 

29

 

                      The information required by this Item is included under Item 8 of this Report.

 

 

 

(a)(3)	EXHIBITS.
3.1	The Company’s Certificate of Incorporation, as amended (Incorporated by reference to Exhibit 3.1 filed with the Company’s Registration Statement on Form S-3 on July 11, 2000).
3.2	The Company’s Bylaws, as amended and restated as of August 1, 2000, as further amended effective October 30, 2001.
4.2	Indenture between Lattice Semiconductor Corporation and State Street Bank and Trust Company of California, N.A., dated as of November 1, 1999 (Incorporated by reference to Exhibit 4.1 filed with the Company’s Registration Statement on Form S-3 on December 21, 1999).
4.3	Form of Note for the Company’s 43/4% Convertible Subordinated Notes (Incorporated by reference to Exhibit 4.3 filed with the Company’s Registration Statement on Form S-3 on December 21, 1999).
10.10	* Form of Stock Option Agreement (Incorporated by reference to Exhibit 10.9, File No. 33-31231).
10.11	* Employment Letter dated September 2, 1988 from Lattice Semiconductor Corporation to Cyrus Y. Tsui (Incorporated by reference to Exhibit 10.10, File No. 33-31231).
10.15	* 1993 Outside Directors Stock Option Plan (Incorporated by reference to Exhibit 10.15 filed with the Company’s Annual Report on Form 10-K for the fiscal year ended April 3, 1993).
10.16	* Employee Stock Purchase Plan, as amended (Incorporated by reference to Exhibit 10.16 filed with the Company’s Annual Report on Form 10-K for the fiscal year ended April 3, 1993).
10.20	Foundry Venture Side Letter dated September 13, 1995 among Lattice Semiconductor Corporation, United Microelectronics Corporation and FabVen (Incorporated by reference to Exhibit 10.2 filed with the Company’s Current Report on Form 8-K dated September 28, 1995)(1).
10.21	FabVen Foundry Capacity Agreement dated as of August    , 1995 among FabVen, United Microelectronics Corporation and Lattice Semiconductor Corporation (Incorporated by  reference to Exhibit 10.3 filed with the Company’s Current Report on Form 8-K dated September 28, 1995)(1).
10.22	Foundry Venture Agreement dated as of August    , 1995, between Lattice Semiconductor Corporation and United Microelectronics Corporation (Incorporated by reference to Exhibit 10.4 filed with the Company’s Current Report on Form 8-K dated September 28, 1995)(1).
10.23	Advance Production Payment Agreement dated March 17, 1997 among Lattice Semiconductor Corporation and Seiko Epson Corporation and S MOS Systems, Inc. (Incorporated by reference to Exhibit 10.23 filed with the Company’s Annual Report on Form 10-K for the fiscal year ended March 29, 1997)(1).

 

30

 

10.24		* Lattice Semiconductor Corporation 1996 Stock Incentive Plan (Incorporated by reference to Exhibit 4.1 filed on Form S-8 dated November 7, 1996).
10.30		Registration Rights Agreement by and among Lattice Semiconductor Corporation, Morgan Stanley & Co. Incorporated, Goldman Sachs & Co., BancBoston Robertson Stephens Inc. and ABN Amro Incorporated dated as of November 3, 1999 (Incorporated by reference to Exhibit 4.2 filed with the Company’s Registration Statement on Form S-3 on December 21, 1999).
10.31		Asset Purchase Agreement by and between Agere Systems Inc. and Lattice Semiconductor Corporation, dated December 7, 2001 (Incorporated by reference to Exhibit 10.1 filed with the Company’s Current Report on Form 8-K filed on December 18, 2001).
10.32		Amendment dated December 21, 2001 to Advance Production Payment Agreement dated March 17, 1997 among Lattice Semiconductor Corporation and Seiko Epson Corporation and S MOS Systems, Inc. (2)
10.33		* 2001 Outside Directors’ Stock Option Plan (Incorporated by reference to Appendix B filed with the Company’s Definitive Proxy Statement on Schedule 14A filed on March 23, 2001).
10.34		* 2001 Stock Option Plan (Incorporated by reference to Appendix C filed with the Company’s Definitive Proxy Statement on Schedule 14A filed on March 23, 2001).
10.35		Intellectual Property Agreement by and between Agere Systems Inc. and Agere Systems Guardian Corporation and Lattice Semiconductor Corporation as Buyer, dated January 18, 2002).
13.1		2001 Annual Report to Stockholders.
21.1		Subsidiaries of the Registrant.
23.1		Consent of Independent Accountants.
24.1		Power of Attorney (see page 32).
(1)  Pursuant to Rule 24b-2 under the Securities Exchange Act of 1934, confidential treatment has been granted to portions of this exhibit, which portions have been deleted and filed separately with the Securities and Exchange Commission.
(2)  Pursuant to Rule 24b-2 under the Securities Exchange Act of 1934, confidential treatment has been granted to portions of this exhibit, which portions have been deleted and filed separately with the Securities and Exchange Commission.
*   Management contract or compensatory plan or arrangement required to be filed as an Exhibit to this Annual Report on Form 10-K pursuant to Item14(c) thereof.
(b)	On November 1, 2001, we filed a report on Form 8-K dated October 30, 2001 announcing the promotion of Steven A. Laub to President and his election to our Board of Directors.
	On December 18, 2001, we filed a report on Form 8-K dated December 7, 2001 announcing that we had entered into an asset purchase agreement with Agere Systems, Inc. dated Decenber 7, 2001.
(c)	See (a)(3) above.
(d)	See (a)(1) and (2) above.

 

31

 

SIGNATURES

 

Pursuant to the requirements of Section 13 or 15(d) of the Securities Exchange Act of 1934, the Registrant has duly caused this Report to be signed on its behalf by the undersigned, thereunto duly authorized, in the City of Hillsboro, State of Oregon, on the 25th of March, 2002.

 

	LATTICE SEMICONDUCTOR CORPORATION
	/s/ Stephen A. Skaggs
	Stephen A. Skaggs, Senior Vice President,
	Chief Financial Officer and Secretary

 

POWER OF ATTORNEY

 

KNOW ALL PERSONS BY THESE PRESENTS, that each person whose signature appears below constitutes and appoints Cyrus Y. Tsui and Stephen A. Skaggs, jointly and severally, his attorneys-in-fact, each with the power of substitution, for him in any and all capacities, to sign any amendments to this Report on Form 10-K, and to file the same, with exhibits thereto and other documents in connection therewith, with the Securities and Exchange Commission, hereby ratifying and confirming all that each of said attorneys-in-fact, or his substitute or substitutes, may do or cause to be done by virtue hereof.

 

Pursuant to the requirements of the Securities Exchange Act of 1934, this Report has been signed below by the following persons on the 25th day of March, 2002 on behalf of the Registrant and in the capacities indicated:

 

Signature		Title
/s/ Cyrus Y. Tsui		Chief Executive Officer and Chairman of the Board (Principal Executive Officer)
Cyrus Y. Tsui
/s/ Steven A. Laub		President and Director
Steven A. Laub
/s/ Stephen A. Skaggs		Senior Vice President, Chief Financial Officer and Secretary (Principal Financial Officer)
Stephen A. Skaggs
/s/ Mark O Hatfield		Director
Mark O. Hatfield
/s/ Daniel S. Hauer		Director
Daniel S. Hauer
/s/ Harry A. Merlo		Director
Harry A. Merlo
/s/ Larry W. Sonsini		Director
Larry W. Sonsini
/s/ Soo Boon Koh		Director
Soo Boon Koh

 

32

 

 

Report of Independent Accountants on

Financial Statement Schedule

 

 

To the Board of Directors of

Lattice Semiconductor Corporation

 

 

Our audits of the consolidated financial statements referred to in our report dated January 30, 2002 appearing in the 2001 Annual Report to Stockholders of Lattice Semiconductor Corporation and subsidiaries (which report and consolidated financial statements are incorporated by reference in this Annual Report on Form 10-K) also included an audit of the financial statement schedule listed in Item 14(a)(2) of this Form 10-K.  In our opinion, this financial statement schedule presents fairly, in all material respects, the information set forth therein when read in conjunction with the related consolidated financial statements.

 

 

Portland, Oregon

January 30, 2002

 

 

 

S-1

 

 

Schedule II

 

 

LATTICE SEMICONDUCTOR CORPORATION

 

VALUATION AND QUALIFYING ACCOUNTS

 

(In thousands)

 

Column A		Column B			Column C			Column D			Column E			Column F
								Charged to
		Balance at			Charged to			other			Write-offs			Balance
		beginning of			costs and			accounts			net of			at end of
Classification		period			expenses			(describe)			recoveries			period
Fiscal period ended December 31, 1999:
Allowance for deferred tax asset		$	1,655		$	—		$	—		$	(1,655	)	$	—
Allowance for doubtful accounts		881			75			650			(23		)	1,583
		$	2,536		$	75		$	650	(1)	$	(1,678	)	$	1,583
Fiscal year ended December 31, 2000:
Allowance for doubtful accounts		$	1,583		$	150		$	—		$	(33	)	$	1,700
		$	1,583		$	150		$	—		$	(33	)	$	1,700
Fiscal year ended December 31, 2001:
Allowance for doubtful accounts		$	1,700		$	(225	)	$	—		$	—		$	1,475
		$	1,700		$	(225	)	$	—		$	—		$	1,475

 

 

(1)  Balance acquired in conjunction with our acquisition of Vantis Corporation on June 15, 1999.

 

 

S-2