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UNITED STATES
SECURITIES AND EXCHANGE COMMISSION
Washington, D.C. 20549

FORM 10-K

Commission File Number 0-19807

SYNOPSYS, INC.
(Exact name of registrant as specified in its charter)

700 East Middlefield Road, Mountain View, California 94043
(Address of principal executive offices, including zip code)

(650) 584-5000
(Registrant's telephone number, including area code)

Securities Registered Pursuant to Section 12(b) of the Act: None

Securities Registered Pursuant to Section 12(g) of the Act:

Common Stock, $0.01 par value
(Title of Class)

Preferred Share Purchase Rights
(Title of Class)

        Indicate by check mark whether the Registrant (1) has filed all reports required to be filed by Section 13 or 15(d) of the Securities Exchange Act of 1934 during the preceding 12 months (or for such shorter period that the Registrant was required to file such reports), and (2) has been subject to such filing requirements for the past 90 days. Yes ý    No o

        Indicate by check mark if disclosure of delinquent filers pursuant to Item 405 of Regulation S-K is not contained herein, and will not be contained, to the best of Registrant's knowledge, in definitive proxy or information statements incorporated by reference in Part III of this Form 10-K or any amendment to this Form 10-K. ý

        Indicate by check mark whether the Registrant is an accelerated filer (as defined in Rule 12b-2 of the Act). Yes ý    No o

        The aggregate market value of the voting and non-voting common equity held by non-affiliates computed by reference to the price at which the common equity was last sold as of the last business day of the Registrant's most recently completed second fiscal quarter was approximately $2,971,050,000. Aggregate market value excludes an aggregate of 43,963,564 shares of common stock held by officers and directors and by each person known by the Registrant to own 5% or more of the outstanding common stock on such date. Exclusion of shares held by any of these persons should not be construed to indicate that such person possesses the power, direct or indirect, to direct or cause the direction of the management or policies of the Registrant, or that such person is controlled by or under common control with the Registrant.

        On January 1, 2005, 146,017,235 shares of the Registrant's Common Stock, $0.01 par value, were outstanding.

DOCUMENTS INCORPORATED BY REFERENCE

        None.

SYNOPSYS, INC.
ANNUAL REPORT ON FORM 10-K
Year ended October 31, 2004

TABLE OF CONTENTS

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PART I

        This Annual Report on Form 10-K, particularly in Item 1. "Business" and Item 7. "Management's Discussion and Analysis of Financial Condition and Results of Operations," includes forward-looking statements within the meaning of Section 27A of the Securities Act of 1933 (the Securities Act) and Section 21E of the Securities Exchange Act of 1934 (the Exchange Act). These statements include, but are not limited to, statements concerning: our business, product and platform strategies expectations regarding previous and future acquisitions; completion of development of our unfinished products or further development or integration of our existing products; expectations regarding bookings, revenue, earnings, changes in operating expenses, cash flows, gross margin and operating margin in fiscal 2005; continuation of current industry trends towards vendor consolidation; expectations regarding our license mix; expectations regarding future maintenance revenue; expectations regarding customer interest in more highly integrated tools and design flows; expectations of the success of our intellectual property and design for manufacturing initiatives; expectations regarding changes in our upfront and time-based revenue in fiscal 2005; expectations regarding revenue seasonality; and our expectations of our future liquidity requirements. Our actual results could differ materially from those projected in the forward-looking statements as a result of a number of factors, risks and uncertainties discussed in this Form 10-K, especially under the caption "Factors that May Affect Future Results," in Item 7 in this Form 10-K. The words "may," "will," "could," "would," "anticipate," "expect," "intend," "believe," "continue," or the negatives of these terms, or other comparable terminology and similar expressions identify these forward- looking statements. The information included herein is given as of the filing date of this Form 10-K with the Securities and Exchange Commission (SEC) and future events or circumstances could differ significantly from these forward-looking statements. Furthermore, we assume no obligation, and do not intend, to update these forward-looking statements except as required by law.

Item 1. Business

Introduction

        Synopsys, Inc. (Synopsys) is a world leader in electronic design automation (EDA) software for semiconductor design. We deliver technology-leading semiconductor design and verification software platforms and integrated circuit (IC) manufacturing software products to the global electronics market, enabling the development and production of complex systems-on-chips (SoCs). We also provide intellectual property (IP) and design services to simplify the design process, and accelerate time-to-market for our customers.

        We incorporated in 1986 in North Carolina and reincorporated in Delaware in 1987. Our headquarters are located at 700 East Middlefield Road, Mountain View, California 94043 and our telephone number is (650) 584-5000. We have more than 60 offices throughout North America, Europe, Japan and Asia.

        Our Annual Reports on Form 10-K, Quarterly Reports on Form 10-Q, Proxy Statements relating to our annual meetings of stockholders, Current Reports on Form 8-K and amendments to these reports and filings made by our executive officers and directors are available on our Internet website (www.synopsys.com). We post these reports to our website as soon as practicable after we file them with the SEC. The contents of our website are not part of this Form 10-K.

The Role of EDA in the Electronics Industry

        Technology advances in the semiconductor industry have steadily increased the feature density, speed, power efficiency and functional capacity of semiconductors (also referred to as integrated circuits, ICs or chips).

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Since the early 1960s, steadily decreasing feature widths (the widths of the wires imprinted on the chip that form the transistors) and other developments have enabled IC manufacturers to follow "Moore's law," approximately doubling every two years the number of transistors that can be placed on a chip. As a result, state-of-the-art ICs now hold over one hundred million transistors and have feature widths of 90 nanometers (billionths of a meter), going to 65 nanometers and below.



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Microprocessors operating at more than 4 gigahertz, a speed unheard of only a few years ago, are readily available today.



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Chips have become more power efficient to address demand for smaller and more powerful handheld devices such as cell phones, digital cameras, music players and personal digital assistants.



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Increasingly, single SoCs can handle functions formerly performed by multiple ICs attached to a printed circuit board.

        Combined, these advances in semiconductor technology have driven development of lower cost, higher performance computers, wireless communications networks, hand held devices, Internet routers and a wealth of other electronic devices. Each advance, however, has introduced new challenges for all participants in semiconductor production, from designers and manufacturers to equipment manufacturers and EDA software suppliers, such as Synopsys.

The IC Design Process

        EDA software is central to the IC design process, enabling designers to design complex semiconductors by using a high-level, abstract description of the function of the chip. EDA software is used to automatically translate this description into successively more detailed forms, and to verify at each stage in the design process that the chip's design is sound and that the chip when manufactured will function as originally intended.

        In simplified form, the IC design process consists of system design, register transfer level design, logic design, functional verification, physical design and physical verification.

        System Design.    In system design, the designer describes the chip's desired functions in very basic terms using a specialized high-level computer language, typically C++ or System C. This phase yields a relatively high-level behavioral model of the chip.

        Register Transfer Level (RTL) Design.    RTL design is the process of capturing the intended design functionality created at the system level using a specialized high-level computer language, typically Verilog or VHDL. This is the stage where the functionality of the final design is captured in enough detail to begin simulation and verification and determine that the final product will function as expected in the verification phase.

        Logic Design.    Logic design, or "synthesis," programs convert the RTL code into a logical diagram of the chip, and produce a data file known as a net list describing the various groups of transistors, or gates, to be built on the chip. Related programs insert the additional circuitry into the design that will be needed to test the chip after manufacture. In a growing number of designs, designers are increasingly performing "design planning" in which the designer determines the location of the major functional "blocks" on the SoC prior to logic synthesis.

        Functional Verification.    At the RTL and gate level of IC design, the designer uses functional verification tools such as RTL simulators and testbench automation and other verification tools to simulate large sets of inputs that a given IC design might confront in a real-life operation. By running these extensive tests, the designer can verify that the design will function as intended.

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        Physical Design.    In the physical design stage, the designer plans the physical location of all of the transistors and each of the wires connecting them with "place and route" products. The designer first determines the location on the chip die for each block of the chip, as well as the location for each transistor within each block, a process known as "placement." In many designs, placement is performed in conjunction with logic synthesis, a process known as "physical synthesis." After placement the designer adds the connections between the transistors, a process known as "routing." The output of place and route programs is one or more data files that can be read by physical verification or mask data preparation programs.

        Physical Verification.    Before sending the chip design files to a manufacturer for fabrication, the designer must perform a series of further verification steps, checking to make sure that the final design complies with the specific requirements of the fabrication facility that will manufacture the chip. The designer may need to add features to the design to ensure that the chip can be manufactured successfully. The completion of this final phase is called "tapeout."

        In actual chip design, each of these steps has a number of additional elements, and designers often undertake the various design and verification steps in a different order than described above, and repeat one or more steps (particularly functional and physical verification) multiple times. Further, several of the steps, especially logic design and physical design, are becoming more integrated with each other. If at any stage of the process the designer determines the chip design will not perform as intended, the designer must go back one or more steps and correct the problem, then continue through subsequent steps. Recreating a chip's logic design, performing simulation over again, and repeating other steps all take time. Each such iteration adds significant costs and makes it more difficult for the designer to meet time-to-market goals.

Current Issues Facing IC Designers

        As chip technology continues to advance, our customers are seeking to maximize the quality of results of their IC design efforts, while minimizing the costs of achieving these results and shortening the time needed to launch the manufactured IC, as follows:

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Quality of Results. Customers are concerned about differentiating their chips from their competitors' in a number of areas, including size or area, speed, functionality, power consumption and performance. The designer must balance each issue against the others, making key tradeoff decisions—often through multiple iterations—to reach a final design. As chips become more complex and manufacturing geometries shrink, this balancing of factors becomes disproportionately more difficult, and requires designers to successfully address technical issues, including:



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Timing closure: achieving consistency between the speed of the chip at the logic design phase and the speed of the chip at the physical design phase;



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Signal integrity: ensuring chip performance is not affected by unintended electrical effects, like cross-talk and other forms of interference, that occur as the wires on a chip get more narrow and closer together;



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Power management: reducing the chip's power consumption, an important objective for chips to be used in battery-operated devices, particularly in the case of laptop computers and cell phones where both longer battery life and lower power drain in standby mode is critical;



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Design for test: embedding circuits in the design that allow the chip, once manufactured, to be tested rapidly and at a reasonable cost;



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Verification: verifying that the chip will perform as intended, which has become the single most time-consuming and resource intensive aspect of overall design;

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Manufacturability: faithfully translating the design produced by EDA tools into a manufacturable pattern of wires and transistors on the chip has become significantly more difficult as a result of decreasing feature widths and increasing feature density; and



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Yield: ensuring that an acceptable number of good chips per wafer can be manufactured successfully.



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Cost of Results. Customers are continually seeking to constrain their costs, including costs of design, masks, equipment, facilities and support, all of which typically increase as chips become more complex. The higher the cost, the higher the expected volume of chips the customer must sell to make a given chip project profitable. Faced with increasing costs, our customers continue to focus intensely on controlling their research and development and manufacturing costs, including their EDA software costs and maximizing their yield in manufacture. As a result, many of our customers have begun consolidating suppliers to improve their purchasing terms and, more importantly, to gain the benefits of better integrated products.



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Time to Results. Finally, customers are seeking to improve the predictability of their production schedule. Economic pressures, competition and continuing innovation continue to shorten the life cycle of electronic products. Accordingly, time-to-market is critical to a product's commercial success. The design time for a product's IC components is a major determining factor of that product's time-to-market. Accordingly, our customers require EDA products that can address the challenges described above while reducing overall design time.

Strategy

        We provide products and services that help our customers design leading-edge ICs while maximizing achievement of their quality of results, cost of results and time to results goals.

        Historically, customers have purchased individual "point tools" to complete one or more tasks or sets of tasks in the design process, dealing internally with moving from one design environment or data set to the next, while integrating various products—or even developing design tools—themselves where necessary. However, with the increasing complexity of IC design, cost pressures and ever smaller market windows, customers require broader solutions with greater performance from fewer vendors at lower costs.

        To meet this need, we have combined our individual products—many of which lead their respective categories—into platforms, or collections of products that are integrated through the use of common interfaces, data sets and other technologies, to deliver a comprehensive, faster and more reliable design flow. In fiscal 2003, we released our Galaxy™ Design and Discovery™ Verification platforms, which together provide complete implementation and verification solutions to our customers. In fiscal 2004, we delivered the Galaxy 2004 platform, providing full, cross-platform correlation in area, timing, power, signal integrity and test, as well as significant speed and capacity improvement. We also delivered substantial improvements to the capabilities, speed, capacity and accuracy of our Discovery Verification platform.

        To help our customers better manage time, cost and risk, we have also continued to invest in pre-designed, pre-verified and reusable intellectual property blocks our customers can use rather than build internally. These blocks include our DesignWare® Foundation Library of reusable, basic chip elements which can be pulled into designs during logic synthesis, our DesignWare Verification Library of reusable chip function models to accelerate simulation and verification, and our DesignWare Cores that implement many of the most important industry standards for digital and analog connectivity, including USB and PCI Express. We also provide professional services to assist our customers with their most difficult design challenges.

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        Finally, recognizing the challenges of manufacturing at feature widths smaller that the wavelength of light, and envisioning the benefits of taking manufacturing and yield issues into account during the design process, we have also continued to invest in our portfolio of Design for Manufacturing tools and technologies.

Organization

        We operate in a single segment and are currently organized into four primary groups: Implementation, Verification, Silicon Engineering and Solutions.

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Implementation Group: develops and markets the products included in the Galaxy Design Platform and related products.



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Verification Group: develops and markets the products included in the Discovery Verification Platform and related products.



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Silicon Engineering Group: focuses on our Design for Manufacturing initiatives and analog/mixed-signal design and verification products.



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Solutions Group: develops and markets our DesignWare® portfolio of pre-designed IP solutions for chip designers and provides turnkey IC design and on-site design assistance, among other services.

        Our other groups include Finance, Human Resources and Facilities, Marketing, Worldwide Sales and Worldwide Application Services.

Products and Services

        Our products and services focus on the principal needs of semiconductor designers and, at a business level, are divided into our Implementation, Verification, Silicon Engineering and Solutions groups described above. We provide financial information regarding our products and services under Part II, Item 7. Management's Discussion and Analysis of Financial Condition and Results of Operations—Results of Operations—Revenue—Product Groups, incorporated by reference here.

Implementation Group

        Galaxy Design Platform.    Our Galaxy Design Platform includes our logic synthesis, physical synthesis, physical design, timing analysis, signal integrity analysis and physical verification products, as well as certain analog and mixed-signal tools, including:

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Design Compiler® logic synthesis product, used by a broad range of IC design companies to optimize their designs for performance and area. With our Galaxy 2004 platform release, our Design Compiler product is up to three times faster than last year's release, has up to 25% more design capacity, and now supports System Verilog, an emerging hardware design language.



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Physical Compiler® physical synthesis product, which unites logic synthesis and placement functionality and addresses critical timing problems encountered in designing advanced ICs and SoCs. In fiscal 2004, we significantly improved the Physical Compiler product's run time and capacity.



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Module Compiler™ data path design product, which allows designers to reuse their datapath structures to obtain the best implementation for their designs.



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Power Compiler™ power management product, which helps designers manage and verify power consumption at different stages of the design process. The 2004 version of our Power Compiler product is up to ten times faster than the previous version.

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DFT Compiler™ design testing product, which inserts functional and test logic required to enable efficient, high-coverage testing of the chip after manufacture.



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JupiterXT™ design planning or floorplanning product, that allows designers to quickly partition their chip design into functional blocks that can be separately optimized for logic and physical design. The 2004 version of our JupiterXT product has two times the capacity, and creates a detailed floorplan three times faster, than the previous version..



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Apollo™ basic physical design product used for the placement and routing of a chip.



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Astro™ advanced physical design system, which enables optimization, placement and routing while concurrently accounting for physical effects. Our fiscal 2004 release of the Astro tool runs up to two times faster and has up to a 40% increase in capacity.



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PrimeTime®/PrimeTime® SI timing analysis products that measure and analyze the speed at which a design will operate when it is fabricated. The PrimeTime SI tool analyzes the effect of cross-talk and noise on timing, an increasingly important issue at chip geometries below 180 nanometers. The 2004 version of our PrimeTime tool runs up to three times faster and has up to three times the capacity as the prior version.



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Tetra Max® test pattern generation product family which automatically generates high-quality test vectors to improve the design process.



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Star-RCXT™ extraction solution for analyzing IC layout data and determining key electrical characteristics of a chip, such as capacitance and resistance.



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Hercules™ physical verification product family, which performs hierarchial design-rule checking, electrical rule checking, and layout versus schematic verification. During fiscal 2004, we delivered a faster version of the Hercules tool with higher multi-CPU scalability and broader foundry support.



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Milkyway™ Database, a common design data repository which enables better interoperability among implementation and analysis tools. Storing design data in this single database with rapid read/write access can reduce data translation times between tools and inconsistent interpretations of diverse data. Interfaces to our open Milkyway database have been made available to our customers and other EDA vendors to reduce integration costs for our customers and advance tool interoperability in the industry.

        The Galaxy Design Platform provides our customers a single, integrated IC design solution based on leading individual products and incorporating common libraries and consistent timing, delay calculation and constraints throughout the design process. The platform uses our open Milkyway database and allows designers the flexibility to integrate internally developed and third-party tools. With this advanced functionality, common foundation and flexibility, our Galaxy Design Platform helps reduce design times, decrease integration costs and minimize the risks inherent in advanced, complex IC designs. During fiscal 2004, we released the Galaxy 2004 platform, the latest version of the Galaxy Design Platform, which delivers significantly improved quality of results, time to results and cost of results through greater correlation among the platform's individual products in addressing area, timing, power, signal integrity and test issues. We also introduced our Galaxy Power solution in fiscal 2004, offering designers the ability to improve the power efficiency of their ICs.

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Verification Group

        Discovery Verification Platform.    Our Discovery Verification Platform includes our verification and simulation products. The increasing size and complexity of today's ICs and SoCs have vastly increased the time and effort required to verify chip designs, with verification estimated to consume 60% to 70% of total design time. As a result, reducing verification "risk" (i.e. minimizing the possibility of finding design "bugs" when the ICs are delivered from the foundry) has become increasingly important to customers. To manage and reduce this verification risk, our Discovery platform combines our simulation and verification products and design-for-verification methodologies, and provides a consistent control environment to significantly improve the speed, breadth and accuracy of our customers' verification efforts.

        Our Discovery Verification Platform includes the following principal products:

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VCS® functional verification product, the engine of the Discovery Verification Platform and often used in simulation "farms" consisting of hundreds of computers. The VCS product includes technologies that support model development, testbench creation, coverage feedback and debugging techniques. Our fiscal 2004 release of the VCS product expands support of our Vera® product, making testbench automation native to VCS, and helping post a two to five times improvement in runtime.



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System Studio system level design product focused on system-level algorithm and architecture design and analysis, as well as the interaction between software and hardware and permits designers to model various architectural alternatives for their chips at a system level.



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Vera® testbench generator, which automates the creation of testbenches, custom models that provide simulation inputs and respond to simulated outputs from the design during verification. Automating this process significantly improves verification quality. The 2004 release of the Vera product is up to 10 times faster than its predecessor and is also available native to the VCS product, providing increased productivity benefits.



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LEDA® design rule checker, which enhances a designer's ability to check a design to ensure it can be for synthesized, simulated, tested and reused.



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Formality® formal verification solution, which compares two versions of a design to determine if they are equivalent. The use of formal verification reduces the need to perform functional verification, which is substantially more time-consuming, thus potentially saving a significant amount of time in the overall design process.



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Magellan™ hybrid formal verification product, which combines functional and formal verification technologies to allow engineers to find deep, corner-case design defects during verification.



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NanoSim® simulation and analysis product for analog and mixed signal verification, which offers circuit simulation, timing and power analysis in a single solution. The NanoSim product is a key component of our Discovery AMS verification solution.



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HSPICE® circuit simulator, which offers high-accuracy, transistor-level circuit simulation, thereby enabling designers to better predict the timing, power consumption and functionality of their designs. During fiscal 2004, we announced enhancements to the HSPICE tool resulting in significant improvements in performance and support for high-frequency and RF IC designs.



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Verification IP reusable IP that are designed to test specific functions and adherence to industry protocols in an IC design, which we believe is becoming increasingly important to more quickly achieving verification sign-off.

        In fiscal 2004, we delivered the Discovery AMS solution, a subset of our verification technologies optimized to perform verification on analog and mixed signal designs.

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Silicon Engineering Group

        Our Silicon Engineering Group develops and markets our products and initiatives relating to design for manufacturing and analog/mixed signal IC design and verification.

        Design for Manufacturing.    We offer a variety of products and technologies used at the intersection of IC design and manufacturing which address a number of issues, principally the need to precisely model structures in small geometry ICs and the problems encountered when using photolithography techniques to manufacture ICs containing feature dimensions smaller than the wavelength of light during production. These products are designed to enhance yield, which is becoming increasingly challenging as chip geometries continue to shrink. In addition to our Hercules product, described above under the Galaxy platform our Design for Manufacturing initiatives include our:

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TCAD products, which precisely model individual structures or devices within an IC design to help ensure manufacturability at small geometries. We see TCAD tools as increasingly important to help customers shorten the time to ramp up their production yields, and therefore reduce their manufacturing costs. In this regard, we have made significant investments to expand our TCAD offering, including our November 2004 acquisition of ISE Integrated Systems Engineering AG, a privately-held Swiss company which offered various TCAD products, including three dimensional devise simulators. We also introduced our Taurus Process Atomistic product which models processes at the atomic level for improved performance.



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Proteus OPC/InPhase optical proximity correction (OPC) products which embed and verify corrective features in an IC design and masks to improve manufacturing results for subwavelength feature width design. OPC changes mask geometries to compensate for distortions caused by optical diffraction and resist process effects. During fiscal 2004, we announced improvements to Proteus to provide near linear scalability.



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Phase Shift Masking Technologies consist of mask design techniques that use optical interference to improve depth-of-field and resolution in subwavelength photolithography for designs at 90 nanometers and below.



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SiVL® (Silicon versus Layout) layout verification product that verifies the layout of a subwavelength IC against the silicon it is intended to produce by reading in the layout and simulating lithographic process effects, including optical, resist and etch effects.



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CATS® mask data preparation product that takes a final IC design and "fractures" or "breaks" it into the physical features that will be included in the photomasks to be used in manufacturing.



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Virtual Stepper® mask qualification product, which checks mask quality and analyzes printability of mask defects, helping to separate true defects from nuisance defects.

        Analog and Mixed-Signal Tools.    The Silicon Engineering Group also manages a number of products described above and functionally included in our Galaxy and Discovery platforms that have advanced analog and mixed-signal design capabilities. These products include the NanoSim and HSPICE circuit simulators. In addition, this category includes our Cosmos™ product, which uses schematic-driven layout technology to place and route full-custom ICs, and our Circuit Explorer optimization and analysis product for complex analog designs.

Solutions Group

        Synopsys' Solutions Group includes our portfolio of IP products and components and our Professional Services Group.

        Intellectual Property Products.    As IC designs continue to grow in size, reusing proven design blocks has become an increasingly important way to reduce overall design cost and cycle time. Because

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verification accounts for such a large proportion of total chip design time, reusing pre-designed and verified IP components can keep projects on schedule by ensuring that the "designed in" portions of the chip are "pre-verified" and thus will not contain errors. The ability to reuse such IP allows IC companies to focus their design teams on designing the chip features that will give its products a competitive advantage. For these reasons, IC designers are consolidating their IP purchases from fewer vendors who can provide a reliable, comprehensive portfolio of proven IP.

        Our IP products include:

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DesignWare Foundation Library is an extensive library of basic chip elements (for example, adders and multipliers) which Design Compiler incorporates into the design during the logic synthesis stage.



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DesignWare Verification Library is our library of popular chip function models used during the verification process of chip design.



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DesignWare Cores are pre-designed and pre-verified digital and mixed-signal design blocks that implement many of the most important industry standards, including USB (1.1, 2.0 and On-The-Go), PCI (PCI, PCI-X and PCI Express), Ethernet and JPEG. During fiscal 2004, we announced availability of DesignWare PCI Express physical layer IP core, enabling lower cost ICs. We also acquired Accelerant Networks, Inc., giving our customers access to SERDES technology and additional connectivity IP solutions. Finally, during the year we acquired Cascade Semiconductor Solutions, Inc., adding their root-and-switch port IP. As a result, we believe we offer the industry's most complete PCI Express portfolio.

        Professional Services.    We provide a comprehensive portfolio of consulting services covering all critical phases of the SoC development process, as well as systems development in wireless and broadband applications. We offer customers a variety of engagement models, from on-site design assistance to help our customers design, verify and/or test their chips and improve their design processes, to full turnkey development and training.

Customer Service and Technical Support

        A high level of customer service and support is critical to the adoption and successful use of our products. We provide technical support for our products through both field- and corporate-based application engineering groups. Customers who purchase Technology Subscription Licenses (TSLs) receive software maintenance services bundled with their license fee. Customers who purchase term licenses and perpetual licenses may purchase these services separately. See Product Sales and Licensing Agreements below.

        Software maintenance services include minor product enhancements we develop, bug fixes and access to our technical support center for primary support. Software maintenance also includes access via electronic mail and the World Wide Web to SolvNet®, our web-based support solution that lets customers quickly seek answers to design questions or more insight into design problems. Our SolvNet solution gives customers access to Synopsys' complete design knowledge database using sophisticated information retrieval technology. Updated daily, it includes documentation, design tips and answers to user questions. Customers can also engage, for additional charges, our application consultants, our worldwide network of product experts, for additional support needs.

Customer Education Services

        We offer training workshops designed to increase customer design productivity while using our products. Workshops cover Synopsys products and methodologies used in our design and verification flows, as well as specialized modules addressing system design, logic design, physical design, simulation and test. We offer regularly scheduled workshops in Mountain View, California; Austin, Texas;

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Marlboro, Massachusetts; Reading, England; Rungis, France; Munich, Germany; Tokyo and Osaka, Japan; Seoul, Korea and other locations. We also schedule on-site workshops worldwide at our customers' facilities or other locations. Approximately 8,750 engineers attended Synopsys workshops during fiscal 2004, compared to approximately 8,500 in fiscal 2003.

Product Warranties

        We generally warrant our products to be free from defects in media and to substantially conform to material specifications for a period of 90 days. We also typically provide our customers limited indemnities with respect to claims that their use of our design and verification software products infringe on United States patents, copyrights, trademarks or trade secrets. We have not experienced material warranty or indemnity claims to date, although we are currently defending some of our customers against claims that their use of one of our products infringes a patent held by a Japanese electronics company.

Support for Industry Standards

        We actively create and support standards that will help our customers increase productivity, improve interoperability of tools from different vendors, and solve design problems. Standards in the EDA industry can be established by formal accredited committees, by licensing made available to all, or through open source licensing.

        Synopsys' products support many formal standards, including the most commonly used hardware description languages, VHDL, Verilog HDL, SystemVerilog and SystemC, as well as numerous industry standard data formats for the exchange of data between our tools, other EDA vendor's products and applications customers develop internally.

        Synopsys is a board member and/or participant in the following major EDA standards organizations:

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Accellera, a not-for-profit formal standards organization that drives language-based standards for systems, semiconductor, and design tool companies;



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the interoperability committee of the EDA Consortium, which helps promote quality and interoperability among EDA products from different vendors;



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the Institute of Electrical and Electronics Engineers (IEEE), a non-profit, technical professional association and a leading developer of global industry standards;



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the Virtual Socket Interface Alliance (VSIA), an industry group that promotes standards that facilitate the integration and reuse of functional blocks of intellectual property; and



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the Open SystemC Initiative (OSCI), a non-profit organization that manages SystemC, a language developed by Synopsys and donated to OSCI, with representation from the systems, semiconductor, IP, embedded software and EDA industries.

        Synopsys' TAP-in^SM program provides interface standards to all companies through an open source licensing model. Synopsys manages changes and enhancements that come from the community of licensees. Synopsys, other EDA companies and EDA customers use these standards to facilitate interoperability of their tools. The standards offered through our TAP-in program include our Liberty™ format for library modeling, SDC for design constraints, SAIF for switching activity, our OpenVera® language for hardware verification, and Open MAST for electromechanical design modeling. Synopsys' common database, Milkyway, is available for tool integration by EDA vendors through our MAP-in^SM program.

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        Synopsys' products are written mainly in the C and C++ languages and utilize industry standards for graphical user interfaces. Our software runs under UNIX operating systems, such as Solaris and HP-UX, and under the RedHat Linux operating system. Synopsys' products run on the most widely used hardware platforms, including those from Sun Microsystems, Hewlett-Packard, IBM and PCs that are based upon Intel and AMD microprocessors.

Sales, Distribution and Backlog

        We market our products and services primarily through direct sales in the United States and principal foreign markets. We typically distribute our products and documentation to customers electronically, but provide physical media (i.e. CD-ROMs) when requested by the customer. We employ highly skilled engineers and technically proficient sales persons in order to understand our customers' needs and explain and demonstrate the value of our products.

        We have sales/support centers throughout the United States, in addition to our Mountain View, California headquarters. Outside the United States, we have sales/support offices in Canada, Denmark, Finland, France, Germany, Hong Kong, India, Israel, Italy, Japan, the Netherlands, the People's Republic of China, Singapore, South Korea, Sweden, Taiwan and the United Kingdom. Our foreign headquarters is located in Dublin, Ireland. Our offices are further described under Part I, Item 2. Properties.

        In limited circumstances, we have used distributors to assist us in the sale of certain products in specified markets. See Note 12 of our Notes to Consolidated Financial Statements in Part II, Item 8. Financial Statements and Supplementary Data for additional information about one of our former distributors.

        In fiscal 2004, 2003 and 2002, foreign revenues represented 45%, 43% and 35%, respectively, of Synopsys' total revenue. Additional information relating to domestic and foreign operations is contained in Note 10 of our Notes to Consolidated Financial Statements in Part II, Item 8. Financial Statements and Supplementary Data. Information relating to risks associated with foreign operations are described in Part II, Item 7. Management's Discussion and Analysis of Financial Condition and Results of Operations—Factors That May Affect Future Results—Stagnation of foreign economies, foreign exchange rate fluctuations or other international issues could adversely affect our performance.

        Historically, our orders and revenue have been lowest in our first quarter and highest in our fourth quarter, with a material decline between the fourth quarter of one fiscal year and the first quarter of the next fiscal year, although the timing of major license renewals can alter this typical trend. However, as a result of the shift in our license model, as more fully described in Part II, Item 7. Management's Discussion and Analysis of Financial Condition and Results of Operations—Results of Operations—Orders and Revenue Seasonality, we expect less revenue seasonality beginning in fiscal year 2005.

        Synopsys' aggregate non-cancelable backlog was approximately $1.48 billion on October 31, 2004, representing an approximately 8% decrease from the end of fiscal 2003. Aggregate non-cancelable backlog includes deferred revenue, operational backlog and financial backlog and excludes all items relating to consulting services. Deferred revenue represents that portion of orders for software products, license maintenance and other services which has been delivered and billed to the customer but on which the revenue has not yet been earned. Operational backlog consists of orders for software products sold under perpetual or term licenses and TSLs with customer-requested ship dates within three months that have not been shipped. Financial backlog consists of future installments under time-based licenses and maintenance which are not yet currently due and payable. Our aggregate backlog at the end of fiscal 2004 including consulting was approximately $1.53 billion, approximately 9% lower than at the end of fiscal 2003.

        We have not historically experienced material order cancellations.

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        See Item 13. Certain Relationships and Related Transactions for information concerning customers accounting for more than 10% of our revenue during fiscal 2004.

Research and Development

        Our future performance depends in large part on our ability to further integrate our design and verification platforms, maintain and enhance our current products, develop new products, and meet an expanding range of customer requirements. Research and development on existing and new products is primarily conducted within each product group. In addition, an Advanced Technology Group within Synopsys' Silicon Engineering Group explores new technologies and maintains strong research relationships outside Synopsys with both industry and academia.

        During fiscal 2004, 2003 and 2002, research and development expenses, net of capitalized software development costs, were $285.3 million, $285.9 million and $225.5 million, respectively. Synopsys capitalized software development costs were approximately $2.7 million, $2.6 million and $1.6 million in fiscal 2004, 2003 and 2002, respectively. We expect sales and marketing expense to increase slightly in fiscal 2005 as a result of increased headcount from acquisitions during fiscal 2004 and higher targeted incentive compensation.

Competition

        The EDA industry is highly competitive. We compete against other EDA vendors and against our customers' own design tools and internal design capabilities. In general, we compete principally on technology leadership, product quality and features (including ease-of-use), time-to-results, post-sale support, interoperability with our own and other vendors' products, price and payment terms.

        Our competitors include companies that offer a broad range of products and services, such as Cadence Design Systems, Inc. and Mentor Graphics Corporation, and companies that offer products focused on one or more discrete phases of the IC design process, such as Magma Design Automation, Inc. Since the recent semiconductor downturn, we have increasingly competed on the basis of payment terms and price. In certain situations, in order to win business we must offer substantial discounts on our products due to competitive factors. In other situations, we may lose potential business to a vendor offering a lower price.

Product Sales and Licensing Agreements

        We typically license our software to customers under non-exclusive license agreements that transfer title to the media only and restrict use of our software to specified purposes within specified geographical areas. The majority of our licenses are network licenses that allow a number of individual users to access the software on a defined network, including, in some cases, regional or global networks. License fees depend on the type of license, product mix and number of copies of each product licensed.

        Under certain circumstances, we provide our customers the right to exchange a portion of the software they initially license for other specified Synopsys products. For example, a customer may use our front-end design products for a portion of the license term and then exchange such products for back-end placement software for the remainder of the term in order to complete the customer's IC design. This practice helps assure the customer's access to the complete design flow needed to design its product. The customer's exchange of product for other existing products, when so provided under the customer agreement, does not alter the timing of recognition of the license fees paid by the customer, which is governed by our revenue recognition policies. The ability to offer this right to customers often gives us an advantage over competitors who offer a narrower range of products, because customers can obtain more of their design flow from a single vendor and because customers then have an opportunity to try additional Synopsys tools before licensing them separately. At the same

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time, because in such cases the customer need not obtain a new license and pay an additional license fee for the use of the additional products, the use of these arrangements could result in reduced revenue compared to licensing the individual products separately without exchange rights.

        We currently offer our software products under two license types: renewable TSLs and perpetual licenses. For a full discussion of these licenses, see Part II, Item 7. Management's Discussion and Analysis of Financial Condition and Results of Operations—Critical Accounting Policies and Results of Operations—Revenue Background.

        With respect to our DesignWare Core intellectual property products, we typically license those products to our customers under nonexclusive license agreements that provide usage rights for specific applications. Fees under these licenses are typically charged on a per design basis plus, in some cases, royalties.

        Finally, our professional services teams typically operate under consulting agreements with our customers with statements of work specific to each project.

Proprietary Rights

        Synopsys primarily relies upon a combination of copyright, patent, trademark and trade secret laws and license and nondisclosure agreements to establish and protect its proprietary rights. Our source code is protected both as a trade secret and as an unpublished copyrighted work. However, third parties may develop similar technology independently. In addition, effective copyright and trade secret protection may be unavailable or limited in certain foreign countries. We currently hold United States and foreign patents on some of the technologies included in our products and will continue to pursue additional patents in the future.

        Under our customer agreements and other license agreements, in many cases we offer to indemnify our customer if the licensed products infringe on a third party's intellectual property rights. As a result, we are from time to time subject to claims that our products infringe on these third party rights. For example, we are currently defending some of our customers against claims that their use of one of our products infringes a patent held by a Japanese electronics company. We believe this claim is without merit and will continue to vigorously pursue this defense.

Employees

        As of October 31, 2004, Synopsys had 4,378 full-time employees, with 2,940 based in North America and 1,438 based outside of North America. Our future financial results depend in part upon the continued service of our key technical and senior management personnel and our continuing ability to attract and retain highly qualified technical and managerial personnel. We participate in a dynamic industry, with significant start-up activity, and our headquarters is located in Silicon Valley, where competition for the most highly skilled technical, sales and management employees is intense.

Item 2. Properties

United States Facilities

        Synopsys' principal offices are located in four adjacent buildings in Mountain View, California, which together provide approximately 400,000 square feet of available space. This space is leased through February 2015. Within one half mile of these buildings, in Sunnyvale, California, Synopsys occupies approximately 200,000 square feet of space in two adjacent buildings under lease through April 2007, and approximately 72,000 square feet of space in a third building under lease through April 2007. We use these buildings for administrative, marketing, research and development, sales and support activities.

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        We own two buildings totaling approximately 230,000 square feet on approximately 43 acres of land in Hillsboro, Oregon. Only one of these buildings is occupied, and is used for administrative, marketing, research and development and support activities. In addition, we lease approximately 80,000 square feet of space in Marlboro, Massachusetts for sales and support, research and development and customer education activities. This facility is leased through January 2009.

        Synopsys owns a third building in Sunnyvale, California with approximately 120,000 square feet, which is leased to a third party through February 2009. Synopsys also owns 34 acres of undeveloped land in San Jose, California and 13 acres of undeveloped land in Marlboro, Massachusetts.

        Synopsys currently leases 32 other offices throughout the United States, primarily for sales and support.

International Facilities

        Synopsys leases approximately 45,000 square feet in Dublin, Ireland for its foreign headquarters and for research and development purposes. This space is leased through April 2026. In addition, Synopsys leases foreign sales and service offices in Canada, Denmark, Finland, France, Germany, Hong Kong, India, Israel, Italy, Japan, the Netherlands, the People's Republic of China, Singapore, South Korea, Sweden, Taiwan and the United Kingdom. We also lease research and development facilities in Armenia, Canada, France, Germany, India, the Netherlands, the People's Republic of China, South Korea, Taiwan and the United Kingdom.

        As a result of acquisitions, we have assumed leases in a number of foreign and domestic locations. Following each acquisition, where feasible, we consolidate the acquired company's employees and operations into our existing local sites. In such cases, we generally seek to sublease the assumed space or negotiate with the landlord to terminate the underlying lease.

        We believe our properties are adequately maintained and suitable for their intended use and that our facilities have adequate capacity for our current needs.

Item 3. Legal Proceedings

        On August 25, 2004, a class action complaint entitled Kanekal v. Synopsys, Inc., et al., No. C-04-3580, was filed in federal district court for the Northern District of California against Synopsys and certain of our officers alleging violations of the Exchange Act. The complaint purports to be a class action lawsuit brought on behalf of persons who acquired Synopsys stock during the period of December 3, 2003 through August 18, 2004. The complaint alleges that the individual defendants caused Synopsys to make false and misleading statements about Synopsys' business, forecasts, and financial performance, and that certain Synopsys officers or employees sold portions of their stock holdings while in the possession of adverse, non-public information. The complaint does not specify the amount of damages sought. In November 2004, the Court appointed a lead plaintiff in the case. As a result, Synopsys expects the plaintiff to file an amended complaint in January 2005. Discovery has not commenced in the case and no trial date has been established. While management intends to defend against these federal securities claims vigorously, and Synopsys does not believe that this lawsuit will have a material effect on Synopsys' financial position, results of operations or cash flows, there can be no assurance as to the ultimate disposition of this lawsuit.

        After the end of fiscal 2004, and in connection with our December 1, 2004 announcement that we have signed agreements to acquire Nassda Corporation (Nassda) and to settle all outstanding litigation between the two companies, a class action complaint entitled Robert Israel v. Nassda Corporation, et. al., No. 4705695, was filed in the Court of Chancery of the State of Delaware naming Nassda, its directors and Synopsys as defendants. The complaint purports to be a class action lawsuit brought on behalf of shareholders of Nassda, other than the defendant directors and their affiliates, who allegedly

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would be injured or threatened with injury if the proposed acquisition of Nassda by Synopsys proceeded forward on the terms announced. The purported class action seeks to enjoin the transaction, or alternatively, damages. The complaint does not specify the amount of damages sought. Synopsys believes the claims in this purported class action are without merit, and intends to defend against them vigorously.

Item 4. Submission of Matters to a Vote of Security Holders

        No matters were submitted for a vote of security holders during the fourth quarter of fiscal 2004.

Executive Officers of the Registrant

        The executive officers of Synopsys and their ages as of December 31, 2004, were:

        Dr. Aart J. de Geus co-founded Synopsys and currently serves as Chairman of the Board of Directors and Chief Executive Officer. Since the inception of Synopsys in December 1986, he has held a variety of positions, including Senior Vice President of Engineering and Senior Vice President of Marketing. From 1986 to 1992, Dr. de Geus served as Chairman of the Board. He served as President from 1992 to 1998. Dr. de Geus has served as Chief Executive Officer since January 1994 and has held the additional title of Chairman of the Board since February 1998. He has served as a Director since 1986. From 1982 to 1986 Dr. de Geus was employed by General Electric Corporation, where he was the Manager of the Advanced Computer-Aided Engineering Group. Dr. de Geus holds an M.S.E.E. from the Swiss Federal Institute of Technology in Lausanne, Switzerland and a Ph.D. in electrical engineering from Southern Methodist University.

        Dr. Chi-Foon Chan joined Synopsys as Vice President of Application Engineering & Services in May 1990. Since April 1997 he has served as Chief Operating Officer and since February 1998 he has

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held the additional title of President. Dr. Chan also became a Director of Synopsys in February 1998. From September 1996 to February 1998 he served as Executive Vice President, Office of the President. From February 1994 until April 1997 he served as Senior Vice President, Design Tools Group, and from October 1996 until April 1997 as Acting Senior Vice President, Design Re-Use Group. In addition, he has held the titles of Vice President, Engineering and General Manager, DesignWare Operations and Senior Vice President, Worldwide Field Organization. From March 1987 to May 1990, Dr. Chan was employed by NEC Electronics, where his last position was General Manager, Microprocessor Division. From 1977 to 1987, Dr. Chan held a number of senior engineering positions at Intel Corporation. Dr. Chan holds an M.S. and a Ph.D. in computer engineering from Case Western Reserve University.

        Steven K. Shevick joined Synopsys in July 1995 and currently serves as Senior Vice President, Finance and Chief Financial Officer. Mr. Shevick was appointed Senior Vice President and Chief Financial Officer in January 2003. From October 1999 to January 2003, he was Vice President, Investor Relations and Legal, General Counsel and Corporate Secretary. From March 1998 to October 1999, he was Vice President, Legal, General Counsel and Assistant Corporate Secretary. From July 1995 to March 1998 he served as Deputy General Counsel and Assistant Corporate Secretary. Mr. Shevick holds an A.B. from Harvard College and a J.D. from Georgetown University Law Center.

        Vicki L. Andrews joined Synopsys in May 1993 and currently serves as Senior Vice President, Worldwide Sales. Before holding that position, she served in a number of senior sales roles at Synopsys, including Vice President, Global and Strategic Sales, Vice President, North America Sales and Director, Western United States Sales. She has more than 18 years of experience in the EDA industry. Ms. Andrews holds a B.S. in biology and chemistry from the University of Miami.

        Dr. Raul Camposano has served as Senior Vice President, Chief Technology Officer and General Manager, Silicon Engineering Group since July 2004. Prior to that time, he was Senior Vice President and Chief Technology Officer from September 2000 to July 2004, and Senior Vice President, General Manager of the Design Tools Group from 1997 through September 2000. Prior to joining Synopsys in 1994, he directed the Design Technology Institute at the German National Research Center for Computer Science (GMD) and was a professor in the Department of Computer Science at the University of Paderborn, Germany. Between 1986 and 1991, Dr. Camposano worked at the IBM T.J. Watson Research Center. He was also a member of the research staff at the Computer Science Research Laboratory at the University of Karlsruhe. Dr. Camposano received a B.S.E.E. degree in 1977 and a diploma in electrical engineering in 1978 from the University of Chile and a Ph.D. in computer science from the University of Karlsruhe in 1981.

        John Chilton has served as Senior Vice President and General Manager of the Solutions Group of Synopsys since August 2003. Prior to that time, he was Senior Vice President and General Manager of the IP and Design Services Business Unit from 2001 to August 2003. From 1997 to 2001, Mr. Chilton served as Vice President and General Manager of the Design Reuse Business Unit. Mr. Chilton received an M.S.E.E. from the University of Southern California and a B.S.E.E. from University of California at Los Angeles.

        Janet S. Collinson has served as Senior Vice President, Human Resources and Facilities since August 2003. From September 1999 to August 2003 she was Vice President, Real Estate and Facilities. Prior to that time she served as Director of Facilities from January 1997 to September 1999. Ms. Collinson received a B.S. in Human Resources from California State University, Fresno.

        Dr. Antun Domic has served as Senior Vice President and General Manager of the Implementation Group since August 2003. Prior to that, Dr. Domic was Vice President and General Manager of the Nanometer Analysis and Test Group from 1999 to August 2003. Dr. Domic joined Synopsys in April 1997, having previously worked at Cadence Design Systems and Digital Equipment Corporation.

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Dr. Domic has a B.S. in Mathematics and Electrical Engineering from the University of Chile in Santiago, Chile, and a Ph.D. in Mathematics from the Massachusetts Institute of Technology.

        Manoj Gandhi has served as Senior Vice President and General Manager, Verification Group since August 2000. Prior to that he was Vice President and General Manager of the Verification Tools Group from July 1999 to August 2000. Prior to that time, he was Vice President of Engineering from December 1997 until July 1999. He holds a B.S. in Computer Science and Engineering from the Indian Institute of Technology, Kharagpur and an M.S. in Computer Science from the University of Massachusetts, Amherst.

        Jay N. Greenberg joined Synopsys in November 2004 as Senior Vice President, Marketing. From March 2003 until joining Synopsys, Mr. Greenberg was President of Green Mountain Solutions, a consulting firm that he also founded. From March 1999 to March 2003 Mr. Greenberg was employed by Taiwan Semiconductor Manufacturing Company, Ltd. (TSMC), where he held the positions of Vice President of Business Development and Vice President of Strategic Marketing. Mr. Greenberg served as Vice President and Senior Partner at Thomas Group, Inc., a consulting firm, from 1987 through 1998. Mr. Greenberg has also held executive, management and technical positions at Memorex, Amdahl and EDS. Mr. Greenberg holds a B.A. from the University of the Pacific in Stockton, California.

        Deirdre Hanford has served as Senior Vice President of Worldwide Applications Services since December 2002. Prior to that time, she was Senior Vice President, Business and Market Development of Synopsys from September 1999 to December 2002. From October 1998 until September 1999, she served as Vice President, Sales for Professional Services and prior to that as Vice President, Corporate Applications Engineering from April 1996 to September 1999. Ms. Hanford received a B.S.E.E. from Brown University and an M.S.E.E. from University of California at Berkeley. Ms. Hanford sits on the American Electronics Association's national board of directors.

        Rex S. Jackson joined Synopsys in February 2003 as Vice President, General Counsel and Corporate Secretary. Prior to joining Synopsys, Mr. Jackson was an investment director with Redleaf Group, Inc., an early stage venture capital firm, from April 2000 through December 2001, and President and CEO of Atlantes Services, Inc., a Redleaf portfolio company, from December 2001 through January 2003. Prior to joining Redleaf, from August 1998 to April 2000, Mr. Jackson was Vice President and General Counsel of AdForce, Inc., a provider of ad management and delivery services on the Internet. Prior to joining AdForce, Mr. Jackson served as Vice President, Business Development and General Counsel of Read-Rite Corporation, a manufacturer of thin film recording heads for the disk and tape drive industries from 1996 to 1998, and as Vice President and General Counsel from 1992 to 1996. Mr. Jackson holds an A.B. degree from Duke University and a J.D. degree from Stanford University.

        There are no family relationships among any Synopsys executive officers or directors.

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PART II

Item 5. Market for Registrant's Common Equity, Related Stockholder Matters and Issuer Purchases of Equity Securities

        The table below sets forth information regarding repurchases of Synopsys common stock by Synopsys during the fiscal quarter ended October 31, 2004.

        All shares were purchased pursuant to a $500 million stock repurchase program originally approved by Synopsys' Board of Directors in July 2001 and renewed in December 2002 and December 2003. Funds are available until expended or until the program is suspended by the Chief Financial Officer or the Board of Directors. Effective and announced on December 1, 2004 the Board of Directors renewed the stock repurchase program, authorizing up to $500 million in additional share repurchases, not including amounts expended prior to such date.

        The remaining information required by Item 5 is set forth in Note 14 of our Notes to Consolidated Financial Statements in Part II, Item 8. Financial Statements and Supplementary Data, incorporated by reference here.

Item 6. Selected Financial Data

Financial Summary

(1)

Synopsys has a fiscal year that ends on the Saturday nearest October 31. Fiscal 2004, 2003, 2002, and 2000 were 52-week years while fiscal 2001 was a 53-week year. For presentation purposes, the consolidated financial statements refer to the calendar month end.

(2)

Includes charges of $1.6 million, $19.8 million, $87.7 million, and $1.7 million for fiscal 2004, 2003, 2002, and 2000, respectively, for in-process research and development. Fiscal 2002 includes merger-related and other costs of $33.5 million and insurance premium costs of $335.8 million related to the Avant! merger.

(3)

Per share data for all periods presented have been adjusted to reflect Synopsys' two-for-one stock split completed on September 23, 2003.

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Item 7. Management's Discussion and Analysis of Financial Condition and Results of Operations

Overview

        The following summary of our financial condition and results of operations is qualified in its entirety by the more complete discussion contained in this Item 7 and by the risk factors set forth below under the caption entitled "Factors That May Affect Future Results."

        Synopsys is a world leader in EDA software for semiconductor design. We deliver technology-leading semiconductor design and verification software platforms and IC manufacturing software products to the global electronics market, enabling the development and production of complex SoCs. We also provide IP and design services to simplify the design process and accelerate time-to-market for our customers.

Fiscal 2004 Business Environment

        We generate substantially all of our revenue from the semiconductor and electronics industries. Our customers typically fund purchases of our software and services out of their research and development (R&D) budgets. As a result, our business is heavily influenced by our customers' business outlook and willingness to invest in new, and increasingly complex, chip designs.

        Beginning in late calendar 2000, the semiconductor industry experienced its steepest and longest downturn of the past 20 years. Semiconductor industry sales dropped approximately 46% from late 2000 to early 2002 and then recovered slowly into 2003. Throughout this period, our customers took many steps to reduce their expenses, including constraining R&D expenditures, reducing the number of design engineers they employed, cutting back on their design starts, purchasing from fewer suppliers, and requiring more favorable pricing, payment and license terms from those suppliers, as well as pursuing consolidation within their own industry. Further, during this downturn, many semiconductor design companies failed or were acquired and the pace of investment in new companies declined.

        The Semiconductor Industry Association reported semiconductor industry growth of approximately 18% in 2003 and estimates growth in 2004 of approximately 29%. Historically, growth in semiconductor sales has been followed by growth in semiconductor R&D spending, which in turn has led to growth in EDA expenditures. This relationship is not precise, however, and in the past there has been a lag of several quarters between an upturn in semiconductor industry sales and growth in EDA spending. At the beginning of fiscal 2004, we based our forecast for the year in part on our expectations that the forecasted continued recovery in semiconductor revenue and improving conditions in the U.S. economy would lead to significantly increased spending on EDA products by our customers. However, by the end of our third fiscal quarter, it became clear that EDA spending growth was not tracking the upturn in the semiconductor industry.

        We believe EDA spending has not tracked the industry's recovery for a number of reasons. First, in light of the severity of the 2000-2002 downturn, we believe customers' intense focus on expense reduction persists, and that they now generally approach spending more conservatively. In addition, the semiconductor industry's recovery has been driven primarily by the consumer electronics market, where product price is a primary competitive factor, further increasing pressure on our customers to control costs, including by limiting their EDA spending.

        In addition to these broader trends, we believe our customers turned more cautious about their own business outlook in mid-calendar 2004 due to a number of factors, including lack of visibility into their own future results, unexpected inventory buildup in the semiconductor supply chain and concerns about the industry's growth prospects in 2005. As a result, we believe our customers became more reluctant to extend or increase their existing commitments to us and to agree to upfront payment terms for multi-year licenses. These developments materially and adversely affected both our bookings and revenue for fiscal year 2004. In particular, lower than expected upfront license bookings adversely

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impacted our third quarter of fiscal 2004 results, since we recognize all revenue from upfront licenses in the quarter they are shipped. Lower than expected time-based license bookings also adversely affected our results for the year and will adversely affect our future results, as a less-than-expected amount was added to our backlog to be recognized in future periods.

        Following the third quarter of fiscal 2004, we re-evaluated customer demand for upfront licenses, which require customers to pay at least 75% of the license fee in the first year. Our customers' increased preference for conserving cash by paying for licenses over time has made upfront payment terms a significantly more difficult negotiating issue. Accordingly, effective in the fourth quarter of fiscal 2004, we shifted our target license mix to consist almost entirely of time-based licenses. For the fourth quarter of fiscal year 2004, upfront licenses constituted approximately 7% of license orders, compared to an average of approximately 24% since our original introduction of time-based licenses in August 2000. This shift negatively impacted revenue, earnings and cash flow from operations for the quarter as many orders which previously would have generated revenue, and in many cases cash, upfront instead were booked as TBLs, contributing primarily to backlog for future quarters.

        Our results in the third quarter and the license mix shift in the fourth quarter resulted in lower revenue, earnings and cash flow from operations in fiscal 2004 compared to fiscal 2003. In addition, due to our further license mix transition we expect revenue, earnings and cash flow from operations for the first three quarters of fiscal 2005 under the new model to be below the comparable quarters under the old, higher upfront model in fiscal 2004. However, we believe making this transition meets our customers' needs while enabling us to better preserve the value of our technology and enhance the predictability of our business.

        We continue to believe that, over the long-term, any growth in EDA spending will continue to depend on growth in semiconductor R&D spending and on continued growth in the overall semiconductor market. The Semiconductor Industry Association has forecasted semiconductor revenues to be flat in 2005 and to grow modestly in 2006. Accordingly, and with our continuing license model shift and our expectation of a relatively low level of major customer license renewals in fiscal 2005 based on scheduled renewal dates, we expect our revenue, earnings and cash flow from operations for fiscal 2005 to be below fiscal 2004.

        Synopsys is under no obligation (and expressly disclaims any such obligation) to update or alter any of the information contained in this Overview, whether as a result of new information, future events or otherwise.

Fiscal 2004 Product Developments

        During fiscal 2004, we announced or introduced a number of enhancements to our products, including:

•

Delivery of our Galaxy 2004 platform, a major enhancement to our original Galaxy Design Platform, offering substantial improvements in speed, capacity, quality of results and process technology support, and representing two years of work integrating products acquired in our acquisition of Avant! Corporation with Synopsys' core products.



•

Release of our Discovery AMS solution, a subset of our verification technologies optimized for verification of analog and mixed-signal designs.



•

Enhancements to our PrimeTime timing analysis product, increasing speed and capacity by up to three times compared to the prior version.



•

Delivery of our Galaxy Power solution, offering designers the ability to improve the power efficiency of their ICs.

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•

Enhancements to our HSPICE circuit simulator, providing up to 20 times better performance and supporting high-frequency and RF IC designs.



•

Improvements to our Proteus OPC product, providing near linear scalability when using industry-leading processors.



•

Availability of DesignWare PCI Express physical layer IP core, enabling lower cost IP.

Fiscal 2004 Financial Performance Summary

•

Orders were $956 million versus $1,368 million in fiscal 2003, reflecting the trends and developments discussed above in "Fiscal 2004 Business Environment" and the timing of a major contract renewal which was expected to be completed in fiscal 2004, but was not completed until the first quarter of fiscal 2005. Our book-to-bill ratio in fiscal 2004 and fiscal 2003 was approximately 0.9 and 1.2, respectively.



•

Revenue was $1,092 million, down 7% from fiscal 2003, due primarily to a lower level of orders than expected in the first three quarters of fiscal 2004, the shift in license mix during the fourth quarter to an almost completely ratable model and a decrease in maintenance revenue.



•

Time-based revenue increased 7% from fiscal 2003 to $663 million, primarily reflecting recognition of revenue on increased time-based orders in fiscal 2003. Upfront license revenue declined 28% from $298 million to $216 million, due primarily to a lower-than-expected level of upfront license orders in the third quarter and to the license model shift effective in the fourth quarter.



•

For the year, we derived approximately 25% of our software revenue from upfront licenses and 75% from time-based licenses, versus approximately 33% and 67%, respectively, during fiscal 2003. The percentage of software revenue from upfront licenses was 29% in the first half of the fiscal year and 20% in the second half of the fiscal year, reflecting lower-than-expected upfront license bookings in the third quarter and the shift from upfront licenses to time-based licenses in the fourth quarter, each of which translated into a reduction in the revenue from upfront license orders. Reflecting this shift, during the fourth quarter, approximately 90% of our revenue was derived from backlog attributable to prior period time-based license bookings.



•

Maintenance revenue declined by 23% from $220 million in fiscal 2003 to $170 million, primarily reflecting the lower-than-expected level of upfront license orders, which led to a lower level of new maintenance orders, the shift of some upfront licenses to TSLs (under which maintenance is included with the license fee and therefore is not reported separately), and non-renewal of maintenance by certain customers compared to fiscal 2003.



•

Professional service and other revenue, at $43 million, increased slightly from $41 million for fiscal 2003, primarily as a result of customers' continued use of outside consultants to augment their internal staff and to assist in implementing their advanced IC designs.



•

Net income was $74 million compared to $150 million in the fiscal 2003, primarily due to lower revenue and other income, an increase in cost of services revenues due to increased field support headcount and higher amortization of intangible assets from acquisitions.



•

Cash provided by operations for fiscal 2004 was $264 million compared to $392 million for fiscal 2003, driven primarily by lower orders and reported revenues compared to fiscal 2003, cash disbursements for foreign income taxes, higher general and administrative expenses and workforce realignment expenses.



•

We repurchased 16.9 million shares of our common stock in fiscal 2004 for approximately $423 million. In December 2004, after the end of the fiscal year, our Board renewed the stock

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buyback program, restoring the authorization to repurchase up to $500 million of our common stock.

Fiscal 2004 Acquisitions

        In fiscal 2004, we acquired (i) Accelerant Networks, Inc. (Accelerant) to enhance our standards-based IP solutions; (ii) Cascade Semiconductors, Inc. (Cascade), to augment our IP portfolio of PCI Express products; and (iii) the technology assets of Analog Design Automation, Inc. (ADA) to expand our analog and mixed-signal offerings. In addition, in fiscal 2004 we completed one additional acquisition and two additional asset acquisition transactions we do not consider material for financial statement purposes. After the fiscal year end, we completed the acquisition of ISE Integrated Systems Engineering AG (ISE), broadening our TCAD product line and announced the proposed acquisition of Nassda Corporation, which would settle our outstanding litigation and enhance our circuit simulation offerings.

Critical Accounting Policies

        We base the discussion and analysis of our financial condition and results of operations upon our audited consolidated financial statements, which we prepare in accordance with accounting principles generally accepted in the United States of America. In preparing these financial statements, we must make estimates and judgments that affect the reported amounts of assets, liabilities, revenues and expenses and related disclosure of contingent assets and liabilities. On an on-going basis, we evaluate our estimates based on historical experience and various other assumptions we believe are reasonable under the circumstances. Our actual results may differ from these estimates.

        The accounting policies that most frequently require us to make estimates and judgments, and therefore are critical to understanding our results of operations, are:

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Revenue recognition;



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Valuation of intangible assets and goodwill;



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Income taxes; and



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Allowance for doubtful accounts.

        Revenue Recognition.    We have designed and implemented revenue recognition policies in accordance with Statement of Position (SOP) 97-2, Software Revenue Recognition, as amended by SOP 98-9, Modification of SOP 97-2, Software Revenue Recognition, With Respect to Certain Transactions.

        With respect to software sales, during fiscal 2004, we utilized three license types:

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Technology Subscription Licenses (TSLs) are for a finite term, on average approximately three years, and generally provide the customer limited rights to receive, or to exchange certain quantities of licensed software for, unspecified future technology. Maintenance is bundled for the term of the license and not purchased separately.



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Term Licenses are also for a finite term, usually three years, but do not provide the customer any rights to receive, or to exchange licensed software for, unspecified future technology. Customers purchase maintenance separately for the first year and may renew annually for the balance of the term. The annual maintenance fee is typically calculated as a percentage of the net license fee.



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Perpetual Licenses, which continue as long as the customer renews maintenance, plus an additional 20 years. Perpetual licenses do not provide the customer any rights to receive, or to exchange licensed software for, unspecified future technology. Customers purchase maintenance separately for the first year and may renew annually. The annual maintenance fee for purchases

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under $2 million is typically calculated as a percentage of the list price of the licensed software. For purchases over $2 million, the annual maintenance fee is typically calculated as a percentage of the net license fee.

        We sometimes refer to TSLs and term licenses, either individually or collectively, as "renewable licenses" because the customer must purchase an extension or a new license in order to continue using the software after the specified term of the contract expires. In a renewal transaction, we may either replace the pre-existing arrangement with an entirely new arrangement or maintain two agreements. Where we replace the existing agreement, we often supersede the original arrangement and thereafter deliver software and recognize revenue based upon the type of license reflected in the new agreement. Where we maintain two agreements, we recognize revenue on the new incremental agreement based upon the new license type purchased. If we grant extended payment terms (as discussed below), we recognize license revenue as payments become due and payable.

        Customers occasionally convert their existing TSLs to perpetual licenses, paying an incremental fee which we recognize upon contract signing in accordance with AICPA Technical Practice Aid (TPA) 5100.73, assuming all other revenue recognition criteria have been met. In some situations, the contract converting the TSL to a perpetual license is modified to such an extent that a new arrangement exists. The changes to the contract may include increases or decreases in the total technology under license, changes in payment terms, changes in license terms and other pertinent factors. In these situations, we account for all of the arrangement fee as a new sale and recognize revenue when all other revenue recognition criteria have been met.

        We report revenue in three categories: upfront license, time-based license and service.

        Upfront license revenue includes:

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Perpetual licenses.  We recognize the perpetual license fee in full if, upon shipment of the software, payment terms require the customer to pay at least 75% of the perpetual license fee within one year from shipment and all other revenue recognition criteria are met. For perpetual licenses in which less than 75% of the license fee is payable within one year from shipment, we recognize the revenue as customer installments become due and payable.



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Upfront term licenses.  We recognize term license fees in full if, upon shipment of the software, payment terms require the customer to pay at least 75% of the term license fee within one year from shipment and all other revenue recognition criteria are met.

        Time-Based License (TBL) revenue includes:

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Technology Subscription Licenses.  We typically recognize revenue from TSL license fees (which include bundled maintenance) ratably over the term of the license period. However, where we offer extended payment terms (i.e., where less than 75% of the TSL license fees are due within one year from shipment), we recognize revenue from TSLs in an amount equal to the lesser of the ratable portion of the entire fee or customer installments as they become due and payable.



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Term Licenses with Extended Payment Terms.  For term licenses where less than 75% of the term license fee is due within one year from shipment, we recognize revenue as customer installments become due and payable.

        Service revenue includes:

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Maintenance Fees Associated with Perpetual and Term Licenses.  We generally recognize revenue from maintenance associated with perpetual and term licenses ratably over the maintenance term.



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Professional Service Fees.  We generally recognize revenue from consulting and training services as services are performed and accepted.

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        We allocate revenue on software transactions (referred to as "arrangements") involving multiple elements to each element based on the respective fair values of the elements. Our determination of fair value of each element is based on vendor-specific objective evidence (VSOE). We limit our assessment of VSOE for each element to the price charged when the same element is sold separately.

        We have analyzed all of the elements included in our multiple-element arrangements and determined that we have sufficient VSOE to allocate revenue to the maintenance components of our perpetual and term license products and to consulting. Accordingly, assuming all other revenue recognition criteria are met, we recognize revenue from perpetual and term licenses upon delivery using the residual method in accordance with SOP 98-9, recognize revenue from maintenance ratably over the maintenance term and recognize consulting revenues as the related services are performed.

        We make significant judgments related to revenue recognition. Specifically, in connection with each transaction involving our products, we must evaluate whether (i) persuasive evidence of an arrangement exists, (ii) delivery has occurred, (iii) our fee is fixed or determinable, and (iv) collectibility is probable. We apply these criteria as discussed below.

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Persuasive Evidence of an Arrangement Exists. Our customary practice is to have a written contract, signed by both the customer and us, or a purchase order from those customers that have previously negotiated a standard end-user license arrangement or volume purchase agreement with us prior to recognizing revenue on an arrangement.



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Delivery Has Occurred. We deliver software to our customers physically or electronically. For physical deliveries, our standard transfer terms are typically FOB shipping point. For electronic deliveries, delivery occurs when we provide the customer access codes or "keys" that allow the customer to take immediate possession of software.



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The Fee is Fixed or Determinable. Our determination that an arrangement fee is fixed or determinable depends principally on the arrangement's payment terms. Our standard payment terms require 75% or more of the arrangement fee to be paid within one year. Where these terms apply, we regard the fee as fixed or determinable, and we recognize revenue upon delivery (assuming all other revenue recognition criteria are met). If the payment terms do not meet this standard, which we refer to as "extended payment terms," we do not consider the fee to be fixed or determinable and generally recognize revenue when customer installments are due and payable. In the case of a TSL, we recognize revenue ratably even if the fee is fixed or determinable, due to application of other revenue accounting guidelines relating to maintenance services and arrangements that include rights to unspecified future technology.



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Collectibility is Probable. To recognize revenue, we must judge collectibility of the arrangement fees, which we do on a customer-by-customer basis pursuant to our credit review policy. We typically sell to customers with whom we have a history of successful collection. For a new customer, we evaluate the customer's financial position and ability to pay and typically assign a credit limit based on that review. We increase the credit limit only after we have established a successful collection history with the customer. If we determine at any time that collectibility is not probable based upon our credit review process or the customer's payment history, we recognize revenue on a cash-collected basis.

        Valuation of Intangible Assets and Goodwill.    We evaluate our intangible assets for indications of impairment whenever events or changes in circumstances indicate that the carrying value may not be recoverable. Intangible assets consist of purchased technology, contract rights intangibles, customer-installed base/relationships, trademarks and tradenames, covenants not to compete, customer backlog, and other intangibles. Factors that could trigger an impairment review include significant under-performance relative to expected historical or projected future operating results, significant changes in the manner of our use of the acquired assets or the strategy for our overall business or significant

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negative industry or economic trends. If this evaluation indicates that the value of the intangible asset may be impaired, we make an assessment of the recoverability of the net carrying value of the asset over its remaining useful life. If this assessment indicates that the intangible asset is not recoverable, based on the estimated undiscounted future cash flows of the technology over the remaining amortization period, we reduce the net carrying value of the related intangible asset to fair value and may adjust the remaining amortization period. Any such impairment charge could be significant and could have a material adverse effect on our reported financial statements. We did not record any impairment charges on our intangible assets during fiscal 2004. As of October 31, 2004, the carrying amount of our intangible assets, net was $198.1 million.

        We evaluate aggregate goodwill on a quarterly basis for indications of impairment based on our fair value as determined by our market capitalization in accordance with Statement of Financial Standards No. 142 (SFAS 142), Goodwill and Other Intangible Assets. If this evaluation indicates that the value of the goodwill may be impaired, we assess the impairment of the goodwill using the two-step method prescribed by SFAS 142. Any such impairment charge could be significant and could have a material adverse effect on our reported financial statements. We did not record any impairment charges on our goodwill during fiscal 2004. As of October 31, 2004, the carrying amount of our goodwill was $593.7 million.

        Income Taxes.    The relative proportions of our domestic and foreign revenue and income directly affect our effective tax rate. We are also subject to changing tax laws in the multiple jurisdictions in which we operate. As of October 31, 2004, current deferred tax assets, net of current deferred tax liabilities totaled $125.6 million. Non-current deferred tax assets, net of non-current deferred tax liabilities, totaled $146.4 million. We believe it is more likely than not that our results of future operations will generate sufficient taxable income to utilize our net deferred tax assets. We consider future taxable income and ongoing prudent and feasible tax planning strategies in assessing the need for any valuation allowance, and if we determine we would not be able to realize all or part of our net deferred tax assets in the future, we would charge to income an adjustment to the deferred tax assets in the period we make that determination.

        We provide for United States income taxes on the earnings of our foreign subsidiaries unless they are considered permanently invested outside of the United States. As of October 31, 2004, the cumulative amount of earnings upon which United States income taxes have not been provided was approximately $36.3 million.

        Allowance for Doubtful Accounts.    We estimate the collectibility of accounts receivable on an account-by-account basis and establish a specific reserve for any particular receivable when we determine collectibility is not probable. In addition, we provide a general reserve on all accounts receivable, which we calculate as a percentage, determined within a specified range of percentages of the outstanding balance in each aged group. In determining this percentage, we specifically analyze accounts receivable and historical bad debt expense, customer creditworthiness, current economic trends, international exposures (such as currency devaluation), and changes in our customer payment terms to evaluate the adequacy of the allowance for doubtful accounts. If the financial condition of our customers deteriorates, impairing their ability to make payments, we may need to establish additional allowances. As of October 31, 2004, our allowance for doubtful accounts was $7.1 million.

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Results of Operations

Revenue Background

        We generate our revenue from the sale of software licenses, maintenance and professional services. As a result of the application of accounting rules and policies relating to revenue recognition, orders we receive for software licenses and services turn into revenue on our income statements at varying rates. In general, orders for software licenses turn to revenue either at the time the license is shipped (an "upfront license"), or ratably over the term of the license (a "time-based license"). Maintenance orders generally turn to revenue ratably over the maintenance period and professional service orders generally turn to revenue upon completion of contractually agreed upon milestones. A more complete description of our revenue recognition policies can be found above under Critical Accounting Policies.

        Our revenue in any fiscal quarter is equal to the sum of our upfront license revenue, time-based license revenue, maintenance revenue and professional service revenue. Upfront license revenue generally depends on the volume of upfront license orders shipped during the quarter. Time-based license revenue in any quarter is derived almost entirely from TSL orders received and delivered in prior quarters; since our TSL orders generally yield revenue ratably over a typical term of three years, a given TSL order contributes to revenue in the quarter it is booked at most one-twelfth of its aggregate booking value. Maintenance revenue in any quarter is similarly derived largely from maintenance orders received in prior quarters since our maintenance orders generally yield revenue ratably over a typical term of one year. Finally, Professional Service revenue is also derived almost entirely from orders received in prior quarters, since we recognize revenue from professional services when those services are rendered, not when they are booked. Any order or portion thereof that does not turn to revenue in the quarter in which it is received is added to our backlog and generally recognized in future periods. The components of our aggregate backlog are discussed further under Part I, Item 1. Business-Sales, Distribution and Backlog above.

        Given the different revenue impacts of upfront licenses and TSLs, in any given fiscal quarter, our license revenue is very sensitive to the mix of upfront and time-based licenses delivered during the quarter. A TSL order results in significantly lower current-period revenue than an equal- sized order for an upfront license. Conversely, a TSL order will result in higher revenue recognized in future periods than an equal-sized order for an upfront license. For example, on a $120,000 order for an upfront license, we recognize $120,000 of revenue in the quarter the product is shipped and no revenue in future quarters. On a $120,000 order for a three-year TSL shipped on the last day of the quarter, we recognize no revenue in the quarter the product is shipped and $10,000 in each of the twelve succeeding quarters. TSLs also shift maintenance revenue to time-based revenue since maintenance is included in TSLs.

License Order Mix

        Beginning in August 2000, when we adopted TSLs, we maintained a target license mix of approximately 75% TSLs and 25% upfront licenses, based on our expectations of total orders and our assessment of the demand for upfront licenses, which have more front-loaded payment terms than TSLs. From August 2000 through the fourth quarter of fiscal 2004, our average license mix has been 76% time-based licenses and 24% upfront licenses, although the license mix has varied considerably from quarter to quarter. Our license order mix for the last nine fiscal quarters is set forth below:

        The percentage of upfront licenses is driven by a number of factors, including the level of overall license orders, customer demand, preferred customer payment terms and requested customer ship

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dates. The percentages in the third quarter of fiscal 2004 reflect both lower-than-expected upfront orders and a substantially lower-than-expected overall orders total.

        As described above under "Fiscal 2004 Business Environment," for the fourth quarter of fiscal 2004 and beyond, we have adjusted our target license mix from approximately 75% time-based licenses to an almost completely time-based license mix. The figures above for the fourth quarter of fiscal 2004 reflect this shift in our target license mix.

        Our upfront and time-based license agreements sometimes provide the right to exchange a portion of the software initially subject to the license for other specified Synopsys products. The customer's exchange of product, when so provided in the license agreement, does not alter the timing of recognition of the license fees paid by the customer. However, because in such cases the customer need not obtain a new license and pay an additional license fee for the use of the additional products, the use of these arrangements could result in reduced revenue compared to licensing the individual products separately.

Orders

        Total orders in fiscal 2004 were $956 million, a decrease from $1,368 million in fiscal 2003. The decrease in orders reflects the trends and developments discussed above in "Fiscal 2004 Business Environment" and the timing of a major contract renewal, which was expected to occur during fiscal 2004, but which was not completed until the first quarter of fiscal 2005.

Reported Revenue

        The decrease in total revenue for fiscal 2004 compared to fiscal 2003 was due primarily to: (i) a lower level of orders than expected in fiscal 2004; (ii) our shift in the fourth quarter to an almost completely ratable license model; and (iii) a decrease in maintenance revenue. The increase in total revenue for fiscal 2003 compared to fiscal 2002 was primarily due to: (i) contribution of products from the Avant! acquisition, which was completed during the third quarter of fiscal 2002, for all of fiscal 2003; (ii) continued phase-in of the ratable license model; and (iii) license renewals with many of our largest Japanese customers in the second quarter of fiscal 2003, a relatively high proportion of which were perpetual licenses yielding upfront revenue.

        With our further shift in license mix beginning in the fourth quarter of fiscal 2004, we expect total reported revenue for the first three quarters and full fiscal year 2005 under the new more ratable model to be below the comparable periods in fiscal 2004.

Time-Based Revenue

        Since we adopted a license mix of approximately 25% upfront and 75% TBLs in August 2000, our time-based revenue has grown in successive periods in both dollar and percentage terms as TBL orders

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received each fiscal period contribute revenue that is "layered" over the revenue recognized from TBL orders received in prior periods. This effect repeats itself each period in varying degrees until the TBL model is fully phased in.

        The increase in time-based revenue in fiscal 2004 compared to fiscal 2003 was primarily due to this continued phase-in of our ratable license model and to the full-year revenue contribution in fiscal 2004 from a strong level of time-based license orders received during fiscal 2003. The increase in time-based license revenue in fiscal 2003 compared to fiscal 2002 was similarly due primarily to the continued phase-in of the ratable license model and to the increased time-based license sales contributed by Avant! products during the full fiscal year 2003.

        With our shift in the fourth quarter of fiscal 2004 to an almost completely ratable license model, we expect an additional phase-in period during which our time-based revenue should continue to increase in both dollar and percentage terms even if the overall level of TBL orders does not grow, and could grow even if the overall level of TBL orders in any period declines. Over the long term, as we complete this further transition, time-based revenue should more closely track average time-based orders trends.

Upfront Revenue

        The decrease in upfront revenue for fiscal 2004 compared to fiscal 2003 was primarily due to the shift to a higher ratable license model in the fourth quarter of fiscal 2004 and to lower-than-expected upfront orders in the third quarter of fiscal 2004. Upfront license revenue for fiscal 2003 increased compared to fiscal 2002 primarily due to the contribution of Avant! products for the full 2003 fiscal year and license renewals with many of our largest Japanese customers in the second quarter of fiscal 2003, a relatively high proportion of which were perpetual licenses yielding upfront revenue. The percentage of revenue comprised of upfront licenses declined over the three-year period due to the phasing in of our ratable license model begun in August 2000. With our further shift in license mix in the fourth quarter of fiscal 2004, we expect upfront revenue to significantly decrease in fiscal 2005 in both dollar and percentage terms.

Service Revenue

        Our maintenance fees have declined primarily due to our adoption of TSLs, which include maintenance with the license fee and thus contribute no separately recognized maintenance fees. Other

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factors include the pricing of maintenance on perpetual license transactions above $2 million, which is substantially lower than the rates on standard perpetual licenses, and non-renewal of maintenance by certain customers. With our license model shift, we expect more of our maintenance revenue to be included in our overall TSL revenue, and therefore for our separately recognized maintenance revenue to continue to decline.

        Professional service fees grew approximately 5% from fiscal 2003 to fiscal 2004 as customers continued to use our professional services personnel to augment their internal staff and to assist in implementing their advanced IC designs. Professional service revenue decreased significantly from fiscal 2002 to fiscal 2003, reflecting reduced demand for turnkey chip design services.

        During the third and fourth quarters of fiscal 2004, consulting capacity constraints and pricing pressure from customers and competitors constrained our professional service revenue growth. We expect these factors to continue to impact professional service revenue in fiscal 2005.

        Service revenue, as a percentage of total revenue, has posted steady decreases over the past three years due primarily to the inclusion of maintenance services in TSLs described above.

        Orders and Revenue Seasonality.    Historically, our orders and revenue have been lowest in our first quarter and highest in our fourth quarter, with a material decline between the fourth quarter of one fiscal year and the first quarter of the next fiscal year, although the timing of major license renewals can alter this typical trend. In our license model, revenue seasonality has historically resulted principally from the decline in the amount of upfront orders from the fourth quarter of one fiscal year to the first quarter of the next fiscal year. Going forward, however, we expect our shift to an almost completely ratable license model will significantly reduce revenue seasonality.

        Revenue—Product Groups. For management reporting purposes, we organize our products and services into five distinct groups: Galaxy Design Platform, Discovery Verification Platform, Intellectual Property (IP), Design for Manufacturing and Professional Services & Other. The products and services in these groups are described in detail under Part I, Item 1. Business, above.

        The following table summarizes the revenue attributable to these groups as a percentage of total revenue for the last eight quarters. We include revenue from companies or products we have acquired during the periods covered from the acquisition date through the end of the relevant periods. For presentation purposes, we allocate software maintenance revenue, which represented approximately 16% and 19% of our total revenue for fiscal 2004 and fiscal 2003, respectively, to the products to which those support services related. Further, with the adoption of our platform strategy in fiscal 2003, we redefined our product groups and have reclassified prior period revenues in accordance with this grouping to provide a consistent presentation.

        The respective revenue contributions from our different groups has been relatively stable over the eight-quarter period shown in the table above. This stability is principally due to the fact that most of our customers purchase multiple products from us, and do so under TSLs, for which revenue is recognized ratably over the term of the license. Accordingly, significant changes in revenue contribution

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from different groups have been driven primarily by one-time events, such as acquisitions, or by the mix of upfront versus time-based orders received for certain products during a given quarter.

        For example, our Galaxy Design Platform revenue as a percentage of total revenue increased in the second quarter of fiscal 2003 due to a number of large perpetual licenses with our Japanese customers, many of which included a disproportionate amount of products from the Galaxy Design Platform, yielding significant upfront revenue contributions from that product group for that quarter. Similarly, the percentage of revenue from our IP products rose significantly in the third quarter of fiscal 2003 as a result of increased sales of upfront IP licenses during that quarter.

        While we expect our TSL licensing model will continue to lessen quarter-to-quarter variations in revenue in the near-term, we believe our IP and Design for Manufacturing products will, over time, account for increasing percentages of total revenue as a result of our customers' greater acceptance of and reliance upon pre-designed, pre-verified IP components and tools and technologies needed for the manufacture of very small geometry ICs.

Events Affecting Cost of Revenues and Operating Expenses

        Temporary Shutdown of Operations.    As a cost saving measure, we temporarily shut down operations in North America for three days during the first quarter of fiscal 2004, four days during the third quarter of fiscal 2004 and four days during the third quarter of fiscal 2003, resulting in savings of approximately $7.6 million in fiscal 2004 and $4.8 million in fiscal 2003. Operations were not shut down for any days in fiscal 2002. The savings in fiscal 2004 and 2003 relate primarily to salaries and benefits and are reflected in our consolidated financial statements as follows:

        Workforce Reduction.    During the fourth quarter of 2004, the first quarter of fiscal 2003 and the second quarter of fiscal 2002 we reduced expenses by decreasing the number of employees in most departments in domestic and foreign locations. This workforce reduction affected approximately 84 employees in fiscal 2004 (50 employees in the U.S. and 34 employees outside the U.S.), 200 employees in fiscal 2003 (130 employees in the U.S. and 70 employees outside the U.S.) and 175 employees in fiscal 2002 (137 employees in the U.S. and 38 employees outside the U.S.), resulting in charges of approximately $6.6 million in fiscal 2004, $4.4 million in fiscal 2003 and $3.9 million in fiscal 2002. The

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charges in each fiscal year relate primarily to severance and other special termination benefits and are included in our consolidated financial statements as follows:

        Workforce Realignment.    During the fourth quarter of fiscal 2003 and effective in the first quarter of fiscal 2004, we realigned our operations to focus resources on more strategic areas of investment and to become more operationally efficient. This realignment affected a total of 140 employees in the United States and 100 employees outside the United States, in most departments. Charges for severance and other termination benefits totaling $14.9 million were reflected in our consolidated financial statements for fiscal 2003 as follows.

Cost of Revenue

        Cost of revenue includes personnel and related costs to provide product support, consulting services and training. Cost of revenue also includes software production costs, product packaging, documentation, amortization of capitalized software development costs, and amortization of core/developed technology and other intangible assets as described below. Management allocates these expenses, most of which are relatively fixed and do not fluctuate significantly with changes in revenue or license mix, to cost of upfront licenses, cost of time-based licenses and cost of services, based on the mix of orders booked within a given period.

        The increase in cost of revenue in fiscal 2004 compared to fiscal 2003 was primarily due to: (i) an increase in amortization of $9.7 million of core/developed technology recorded as a result of our acquisitions completed in fiscal 2003 and 2004; (ii) an increase of $9.1 million in field support personnel costs due to targeted hiring in the customer support function; and (iii) increased human resources, technology and facilities costs of $3.6 million as a result of the increase in cost of revenue headcount as a percentage of total headcount. This increase was partially offset by a decrease of

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(i) $1.1 million in consulting services; (ii) $2.6 million as discussed above under Workforce Realignment; and (iii) $1.1 million in royalty expense in fiscal 2004 compared to fiscal 2003. Total cost of revenue as a percentage of total revenue increased due to lower revenue during 2004 and increased amortization of intangible assets and deferred stock compensation from acquisitions in fiscal 2003.

        The increase in cost of revenue in fiscal 2003 compared to fiscal 2002 was primarily due to: (i) an increase of $58.9 million in amortization of intangible assets and deferred stock compensation recorded as a result of our acquisitions in fiscal 2003 and 2002; (ii) the cost of our realignment of operations totaling $2.6 million as discussed above under Workforce Realignment; and (iii) additional royalties for in-licensed technology of $1.5 million.

        We expect cost of revenue, excluding amortization of intangible assets and deferred stock compensation allocated to this line item, to increase slightly in fiscal 2005 as a result of increased headcount from acquisitions during fiscal 2004 and higher targeted incentive compensation. We also expect cost of revenue as a percentage of revenue in fiscal 2005 to increase (and gross margin to decrease) due to the expected increase in cost of revenue described above and the expected decrease in revenue in fiscal 2005 compared to fiscal 2004.

        See Amortization of Intangible Assets and Deferred Stock Compensation below for information regarding the amount of amortization charged to cost of revenue for the relevant periods.

Operating Expenses

Functional Allocation of Operating Expenses

        Historically, we allocate certain human resource programs, information technology and facility expenses among our functional income statement categories based on headcount within the functional area. Annually, or upon a significant change in headcount (as in the case of a workforce reduction or realignment) and other factors, management reviews the allocation methodology and the expenses included in the allocation pool. Management conducted such a review with respect to Synopsys' workforce reductions in fiscal 2002 and 2003 and the workforce realignment in fiscal 2004 and with respect to additional expenses from certain worldwide IT and facility programs implemented during fiscal 2002. The resulting expense allocations generally contribute significantly to the fluctuations in functional area expenses from year to year.

Research and Development

        The slight decrease in research and development expense in fiscal 2004 compared to fiscal 2003 reflects an increase of $10.1 million in research and development personnel and related costs as a result of increased investment in research and development activities, offset by: (i) decreased depreciation of $2.2 million as a result of overall decreased capital spending and lower replacement costs compared to fiscal 2003; (ii) severance packages totaling $1.4 million associated with our workforce reduction during fiscal 2003 which were not incurred during fiscal 2004; (iii) a decrease of $1.6 million in consulting services compared to fiscal 2003; and (iv) a reduction of $4.5 million in North America human resources, information technology and facilities costs allocated to research and development expenses as a result of the decrease in research and development headcount as a percentage of total headcount.

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        The increase in research and development expense in fiscal 2003 compared to fiscal 2002 was primarily due to increases of: (i) $30.7 million in research and development personnel and related costs as a result of acquisitions in fiscal 2002 and 2003, including additional employer payroll taxes incurred as a result of stock option exercises during fiscal 2003; (ii) $22.2 million in increased human resources, information technology and facilities costs allocated to research and development as a result of the increase in research and development headcount as a percentage of total headcount; and (iii) $6.3 million as a result of our realignment of operations as discussed above under Workforce Realignment. This increase was partially offset by a decrease in depreciation expense of $2.8 million as a result of capital expenditure control measures implemented in fiscal 2003 and $2.3 million in consulting services incurred in fiscal 2002 that were not incurred in fiscal 2003.

        We expect research and development expense to increase slightly in fiscal 2005 as a result of increased headcount from acquisitions during fiscal 2004 and higher targeted incentive compensation. We also expect research and development expense as a percentage of revenue to increase due to the expected increase in research and development expense described above and the expected decrease in revenue in fiscal 2005 compared to fiscal 2004.

Sales and Marketing

        The decrease in sales and marketing expense in fiscal 2004 compared to fiscal 2003 was primarily due to: (i) a reduction of $4.0 million in variable compensation, driven by reduced orders and shipments in fiscal 2004; (ii) a reduction of $3.0 million in sales and marketing personnel and related costs as a result of decreased headcount due to previous workforce reductions and realignments; and (iii) $4.8 million recorded in the fourth quarter of fiscal 2003 as a result of our realignment of operations as discussed above under Workforce Realignment. This decrease is partially offset by increases of (i) $4.4 million in human resources, information technology and facilities costs allocated to sales and marketing expenses as a result of the increase in sales and marketing headcount as a percentage of total headcount and (ii) $1.2 million related to expanded marketing efforts and charges associated with the cancellation of certain employee-related functions.

        The increase in sales and marketing expense in fiscal 2003 compared to fiscal 2002 was primarily due to: (i) $42.4 million in additional sales and marketing personnel and related costs as a result of acquisitions in fiscal 2002 and 2003, including additional employer payroll taxes incurred as a result of stock option exercises during fiscal 2003, offset by savings from a four-day shutdown of operations in North America; (ii) $4.8 million as a result of realignment charges as discussed above under Workforce Realignment; and (iii) $2.7 million in additional travel expenses related to sales efforts. These increases were partially offset by a decrease of $3.8 million in human resources, technology and facilities costs allocated to sales and marketing expenses as a result of a decrease in sales and marketing headcount as a percentage of total headcount.

        We expect sales and marketing expense to increase slightly in fiscal 2005 as a result of increased headcount from acquisitions during fiscal 2004 and higher targeted incentive compensation. We also expect sales and marketing expense as a percentage of revenue to increase due to the expected increase in research and development expense and the expected decrease in revenue in fiscal 2005 compared to fiscal 2004.

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General and Administrative

        The increase in general and administrative expense in fiscal 2004 compared to fiscal 2003 was primarily due to: (i) the $10.0 million termination fee paid to Monolithic System Technology, Inc. (MoSys) in connection with termination of the acquisition agreement in April 2004 and professional service fees of $5.4 million relating to that transaction and the subsequent litigation; (ii) an increase of $5.0 million in professional service fees relating to other litigation matters; (iii) $4.7 million in facilities costs primarily related to planned facilities consolidation in fiscal 2004; (iv) a loss of $1.1 million related to the sublease of a portion of our Ireland headquarter facility; and (v) a $3.5 million increase in depreciation due to increased capital spending in information technology. This increase was partially offset by a decrease of $3.5 million in human resources, information technology and facilities costs reported under this line item as a result of a decrease in general and administrative headcount as a percentage of total headcount.

        The increase in general and administrative expense in fiscal 2003 compared to fiscal 2002 was primarily due to: (i) $12.8 million in additional general and administrative personnel and related costs as a result of acquisitions in fiscal 2002 and 2003, including additional employer taxes incurred as a result of stock option exercises during fiscal 2003; (ii) $7.0 million increase in depreciation as a result of upgrades to our information technology infrastructure; (iii) an increase of $5.7 million in facilities costs allocated to general and administrative expense due to new leases during the current year and the expiration of a sublease on one of Synopsys' buildings in June 2003; (iv) an increase of $3.7 million in professional services costs, patent prosecution expenditures and litigation; (v) an increase of $2.8 million in maintenance agreements covering software and computing equipment obtained in acquisitions during fiscal 2002 and 2003; and (vi) $1.2 million related to the realignment of operations as discussed above under Workforce Realignment. These increases were partially offset by decreases of (i) $14.2 million in human resources, technology and facilities costs allocated to general and administrative expenses as a result of a decrease in general and administrative headcount as a percentage of total headcount; and (ii) a reduction of $6.6 million in bad debt expense as accounts receivable aging improved from fiscal 2002.

        We expect general and administrative expense to be flat or decrease slightly in fiscal 2005 as a result of continuing cost controls and the absence of certain one-time charges such as those associated with the MoSys transaction, partially offset by higher targeted incentive compensation. However, we expect general and administrative expense as a percentage of revenue to increase due to the expected decrease in revenue in fiscal 2005 compared to fiscal 2004.

        Integration Costs.    Non-recurring integration costs incurred relate to merger activities which are not included in the purchase consideration under Emerging Issues Task Force Number 95-3 (EITF 95-3), Recognition of Liabilities in Connection with a Purchase Business Combination. These costs are expensed as incurred. During fiscal 2002, integration costs were $128.5 million and consisted primarily of: (i) $95.0 million related to the premium for the insurance policy expensed in conjunction with the Avant! merger; (ii) $14.7 million related to write-downs of Synopsys facilities and property under the management approved facility exit plan for the Avant! merger; (iii) $10.7 million related to severance costs for Synopsys employees who were terminated and costs associated with transition employees as a result of the fiscal 2002 mergers; (iv) $1.3 million related to the write-off of software licenses owned by Synopsys which were originally purchased from Avant!; (v) $3.7 million goodwill impairment charge

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related to a prior Synopsys acquisition as a result of the acquisition of Avant!; and (vi) $3.1 million of other expenses including travel and certain professional fees related to the fiscal 2002 mergers.

In-Process Research and Development

        In fiscal 2004 purchased in-process research and development (IPRD) was $1.6 million and represents in-process technologies associated with a fourth quarter acquisition considered immaterial for financial statement purposes. Purchased IPRD of $19.8 million and $87.7 million in fiscal 2003 and 2002, respectively, represents in-process technologies associated with our acquisitions of Numerical in fiscal 2003 and Avant! and inSilicon in fiscal 2002. At the date of each acquisition, the projects associated with the IPRD efforts had not yet reached technological feasibility and the research and development in process had no alternative future uses. Accordingly, these amounts were charged to expense on the respective acquisition date of each of the acquired companies.

        Valuation of IPRD.    The value assigned to acquired in-process technology is determined by identifying products under research in areas for which technological feasibility had not been established as of the acquisition date. The value of in-process technology is then segmented into two classifications: (i) developed technology (completed) and (ii) in-process technology (to-be-completed), giving explicit consideration to the value created by the research and development efforts of the acquired business prior to the date of acquisition and to be created by Synopsys after the acquisition. These value creation efforts were estimated by considering the following major factors: (i) time-based data, (ii) cost-based data and (iii) complexity-based data.

        The value of the in-process technology was determined using a discounted cash flow model similar to the income approach, focusing on the income producing capabilities of the in-process technologies. Under this approach, the value is determined by estimating the revenue contribution generated by each of the identified products within the classification segments. Revenue estimates were based on (i) individual product revenues, (ii) anticipated growth rates, (iii) anticipated product development and introduction schedules, (iv) product sales cycles, and (v) the estimated life of a product's underlying technology. From the revenue estimates, operating expense estimates, including costs of sales, general and administrative, sales and marketing, income taxes and a use charge for contributory assets, were deducted to arrive at operating income. Revenue growth rates were estimated by management for each product and gave consideration to relevant market sizes and growth factors, expected industry trends, the anticipated nature and timing of new product introductions by us and our competitors, individual product sales cycles and the estimated life of each product's underlying technology. Operating expense estimates reflect Synopsys' historical expense ratios. Additionally, these projects will require continued research and development after they have reached a state of technological and commercial feasibility. The resulting operating income stream was discounted to reflect its present value at the date of acquisition.

        The rate used to discount the net cash flows from purchased in-process technology is our weighted-average cost of capital (WACC), taking into account our required rates of return from investments in various areas of the enterprise and reflecting the inherent uncertainties in future revenue estimates from technology investments including the uncertainty surrounding the successful development of the acquired in-process technology, the useful life of such technology, the profitability levels of such technology, if any, and the uncertainty of technological advances, all of which are unknown at this time.

        Numerical.    On March 1, 2003, we acquired Numerical, which specialized in subwavelength lithography-enabling solutions. The IPRD expense related to the Numerical acquisition was $18.3 million. Numerical had five IPRD projects—Phase Shift Masking (PSM), Subwavelength Software, Equipment Software, Cadabra and Computer Aided Transcription System (CATS)—representing 25%, 7%, 6%, 5% and 57%, respectively, of the total IPRD value. These projects were

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expected to be completed shortly following the completion of the merger. PSM, Subwavelength Software and CATS software were completed in fiscal 2003. Our Cadabra® product was released in the first quarter of fiscal 2004. The Equipment Software project consists of in-process technology for multiple products. These products were either completed in fiscal 2003, discontinued, or were integrated with other Synopsys products during fiscal 2004. Expenditures to complete Numerical's acquired in-process technologies approximated the original estimates.

        inSilicon.    On September 20, 2002, we acquired inSilicon, a leading provider of connectivity semiconductor IP used by semiconductor and systems companies to design SoCs that are critical components of innovative wired and wireless products. The IPRD expense related to the inSilicon acquisition was $5.2 million. inSilicon had three IPRD projects—DELA, Peripheral Component Interconnect (PCI) Express and Universal Serial Business Physical (USB PHY)—accounting for 54%, 23% and 23% of the total IPRD value, respectively. These projects were 25%, 67% and 20% complete at the time of acquisition, respectively. During fiscal 2003, Synopsys decided to discontinue the DELA project. PCI Express and USB PHY have been completed. Expenditures to complete inSilicon's acquired in-process technologies approximated the original estimates.

        Avant!.    On June 6, 2002, we acquired Avant!, a leading developer of software used in the physical design and physical verification stages of IC design. The IPRD expense related to the Avant! merger was $82.5 million. The principal in-process technologies were identified based on the following product families:

        These projects were completed during fiscal 2002 and 2003. Expenditures to complete the acquired in-process technologies approximated the original estimates.

        The risks associated with acquired research and development are considered high and no assurance can be made that these products will generate any benefit to us or meet market expectations.

        Amortization of Goodwill, Intangible Assets and Deferred Stock Compensation.    Amortization of intangible assets and deferred stock compensation includes the amortization of the contract rights intangible associated with certain executory contracts, core/developed technology, trademarks, trade names, customer relationships, covenants not to compete and other intangibles acquired in business combinations completed during fiscal 2002, 2003 and 2004. Intangible assets are amortized on a straight-line basis over their useful lives, which range from three to ten years. Deferred stock compensation represents the intrinsic value of unvested stock options assumed in connection with prior year acquisitions. The deferred stock compensation is amortized over the options' remaining vesting period of one to three years. Generally, amortization of deferred stock compensation will decrease over time as the assumed stock options vest, although employee terminations affect the exact timing and

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amount of future amortization of deferred stock compensation. Amortization expense for these assets is included in the consolidated statements of operations as follows:

        The increase in amortization of intangible assets and deferred compensation in fiscal 2004 compared to fiscal 2003 is primarily due to additional amortization of assets acquired in the Numerical acquisition in the second quarter of fiscal 2003 partially offset by the declining amounts of amortization related to deferred compensation recorded in prior year acquisitions. See Note 4 to Notes to Audited Consolidated Financial Statements for a schedule of future amortization amounts.

        The increase in amortization of intangible assets and deferred compensation in fiscal 2003 compared to fiscal 2002 is primarily due to fiscal 2003 and 2002 acquisitions, particularly Avant!, partially offset by a $16.2 million decrease in goodwill amortization as a result of the adoption of SFAS 142 on November 1, 2002 under which goodwill is no longer amortized.

        Impairment of Intangible Assets.    There were no material impairment charges related to intangible assets during fiscal 2004 and 2003.

        In fiscal 2002, we recognized an aggregate impairment charge of $3.8 million to reduce the amount of certain intangible assets associated with prior acquisitions to their estimated fair value. Approximately $3.7 million and $0.1 million are included in integration expense and amortization of intangible assets, respectively, on the consolidated statement of operations. The impairment charge is primarily attributable to the Route Compiler technology acquired from, and goodwill related to, the acquisition of Stanza, Inc. (Stanza) in 1999. During fiscal 2002, we determined that we would not allocate future resources to assist in the market growth of this technology as products acquired in the merger with Avant! provided customers with superior capabilities. As a result, we do not anticipate any future sales of the Stanza product.

        Expensing of Stock Awards.    In December 2004, the Financial Accounting Standards Board (FASB) issued Statement of Financial Accounting Standards No. 123 (revised 2004), Share-Based Payment (SFAS 123R), which will be effective in the fourth quarter of fiscal 2005. SFAS 123R will result in our recognition of substantial compensation expense relating to our employee stock options and employee stock purchase plans. Synopsys currently uses the intrinsic value method to measure compensation expense for stock-based awards to its employees. Under this standard, we generally do not recognize any compensation related to stock option grants we issue under our stock option plans or related to the discounts we provide under our employee stock purchase plans. Under the new rules, we are required to adopt a fair-value-based method for measuring the compensation expense related to employee stock awards; this will lead to substantial additional compensation expense and therefore will have a material adverse effect on our reported results of operations. Note 2 to our Consolidated Financial Statements provides our pro forma net income and earnings per share as if we had used a fair-value-based method similar to the methods required under SFAS 123R to measure the compensation expense for employee stock awards during fiscal years 2004, 2003 and 2002.

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Operating Margin

        Our operating margin declined from approximately 17% in fiscal 2003 to approximately 8% in fiscal 2004, primarily due to the decrease in revenue year over year. As a result of the expected decrease in revenue in fiscal 2005 compared to fiscal 2004 and the expected increase in overall operating expenses described above, we expect our operating margin in fiscal 2005 to be meaningfully lower than in fiscal 2004.

Other Income (Expense), Net

        The decrease in other income (expense) in fiscal 2004 compared to fiscal 2003 was primarily due to reduced investment gains and reduced rental income. The increase in 2003 compared to 2002 was primarily due to the $240.8 million expense in 2002 related to the settlement of the Cadence Design Systems, Inc. (Cadence) litigation.

Liquidity and Capital Resources

        Our source of cash, cash equivalents and short-term investments over the last three years has been from funds generated from our business, including cash on hand from companies we have acquired. Cash, cash equivalents and short-term investments decreased $119.4 million, or 17%, to $579.0 million as of October 31, 2004 from $698.4 million as of October 31, 2003.

        Cash provided by operations was $264.0 million in fiscal 2004 compared to $391.5 million in fiscal 2003. The decrease in cash from operations was driven in part by lower orders and reported revenues in fiscal 2004, as well as by increased use of operating cash as follows: (i) cash disbursements for foreign income taxes of approximately $44.7 million; (ii) payment of $15.4 million for the MoSys acquisition agreement termination fee and associated litigation costs; (iii) disbursements associated with our fiscal 2003 workforce realignment of approximately $15 million; (iv) payments of international value added taxes of approximately $8 million; and (v) increased prepaid maintenance contract expenses for our design and information systems electronic infrastructure. These uses of cash were partially offset by income tax refunds of $28.6 million.

        Accounts receivable, net of allowances, decreased $68.7 million, or 34%, to $132.3 million as of October 31, 2004 from $201.0 million as of October 31, 2003. Days sales outstanding (DSO), calculated based on revenue for the most recent quarter and accounts receivable as of the balance sheet date, decreased to 53 days as of October 31, 2004 from 58 days as of October 31, 2003. The decrease in accounts receivable and DSO was attributable to a $100.7 million reduction in new billings caused by lower orders during fiscal 2004 and longer customer payment terms compared to fiscal 2003, partially offset by a $39.0 million decrease in collections compared to the prior fiscal year.

        Cash provided by operations is in part dependent upon the payment terms on our license agreements. For an upfront license, we require that at least 75% of the license fee be paid within the first year. Conversely, payment terms for time-based licenses are generally extended; typically the license fee is paid quarterly in even increments over the term of the license. Accordingly, we generally

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receive cash from upfront licenses sooner than on time-based licenses. Our lower-than-expected level of up-front orders in the third quarter of fiscal 2004 and further transition to an almost completely ratable license model beginning in the fourth quarter of fiscal 2004 reduced our cash flow from operations for fiscal 2004; we expect this further transition to continue to adversely affect cash flow from operations during fiscal 2005.

        Cash used in investing activities was $172.0 million in fiscal 2004 compared to $258.3 million in fiscal 2003. The decrease of $86.3 million is primarily due to a substantial decrease of cash used for acquisitions and decreased proceeds from the sale of long-term investments.

        Cash used in financing activities was $266.6 million in fiscal 2004 compared to cash provided by financing activities of $74.2 million in fiscal 2003. The decrease of $340.8 million is primarily due to a decrease in proceeds of $178.2 million from the sale of shares pursuant to our employee stock option plans and stock purchase plans during fiscal 2004 and increased purchases of treasury stock of $162.6 million.

        We hold our cash, cash equivalents and short-term investments in the United States and in foreign accounts, primarily in Ireland, Bermuda, and Japan. As of October 31, 2004, we held an aggregate of $202.6 million in cash, cash equivalents and short-term investments in the United States and an aggregate of $376.4 million in foreign accounts. Funds in foreign accounts are generated from revenue outside North America. With the exception of Japan, we currently maintain a policy under APB 23, Accounting for Income Taxes-Special Areas, of permanently reinvesting such funds outside of the United States.

        In April 2004, we entered into a three-year, $250.0 million senior unsecured revolving credit facility. This facility contains financial covenants requiring us to maintain a minimum leverage ratio and specified levels of cash, as well as other non-financial covenants. The facility terminates on April 28, 2007. Borrowings under the facility bear interest at the greater of the administrative agent's prime rate or the Federal funds rate plus 0.50%; however, we have the option to pay interest based on the outstanding amount at eurodollar rates plus a spread between 0.80% and 1.125% based on a pricing grid tied to a financial covenant. In addition, commitment fees are payable on the facility at rates between 0.20% and 0.25% per annum based on a pricing grid tied to a financial covenant. In April 2004, we borrowed and repaid $200 million under the credit facility. As of October 31, 2004, we had no outstanding borrowings under the credit facility and we were in compliance with all covenants.

        In November 2004, Synopsys completed its acquisition of ISE for cash consideration of $100 million.

        On November 30, 2004, Synopsys signed a merger agreement to acquire Nassda Corporation in an all-cash transaction for a purchase price of $7.00 per share. The aggregate consideration is approximately $192 million. At September 30, 2004, Nassda reported cash, cash equivalents and short-term investments of $101.4 million. The transaction is subject to customary regulatory approvals and other closing conditions. In addition, the approval of Nassda's stockholders holding a majority of the outstanding shares of Nassda common stock and approval of the holders of a majority of the outstanding shares of Nassda common stock casting votes affirmatively or negatively on the merger agreement (excluding Nassda's officers and directors, the individual defendants and the related parties of the individual defendants) is required for Nassda and Synopsys to complete the proposed merger. Certain directors, officers and employees of Nassda who own in the aggregate approximately 60% of Nassda's outstanding common shares have agreed to vote in favor of the adoption and approval of the merger agreement. Upon the closing of the acquisition, the Nassda officers, directors and employees who are defendants in the litigation between Synopsys and Nassda will make settlement payments to Synopsys in the aggregate amount of approximately $61 million.

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        We believe that our current cash, cash equivalents, short-term investments and cash generated from operations will satisfy our business requirements for at least the next twelve months.

Contractual Obligations Table

        The following table summarizes our significant contractual obligations as of October 31, 2004. This table excludes amounts already recorded on our balance sheet as current liabilities as of October 31, 2004.

(1)

This commitment relates to the fees associated with the revolving credit facility. Additional information is provided in Note 5 of our Consolidated Financial Statements.

(2)

Operating lease obligations are net of sublease payments to be received. Additional information is provided in Note 6 of our Consolidated Financial Statements.

(3)

Purchase obligations represent an estimate of all open purchase orders and contractual obligations in the course of business for which we have not received the goods or services as of October 31, 2004. Although open purchase orders are considered enforceable and legally binding, the terms generally allow us the option to cancel, reschedule and adjust our requirements based on our business needs prior to the delivery of goods or performance of services.

(4)

Does not include $750,000 of interest payable for bond payable through September 2023. Additional information is provided in Note 5 of our Consolidated Financial Statements. Certain long-term liabilities reflected on our balance sheet, such as unearned revenue, are not presented in this table because they do not require cash settlement in the future.

(5)

We made or are committed to making additional cash expenditures in fiscal 2005 related to business combination transactions; specifically, $95 million related to the acquisition of ISE, net of cash held by ISE, which was paid in November 2004, and approximately $192 million related to the acquisition of Nassda Corporation, which transaction has not closed. Additional information is provided in Note 13 of our Consolidated Financial Statements. These acquisition payments are not included in the table above.

(6)

We are obligated under the contingent consideration provisions related to certain fiscal 2004 business combination transactions to make cash payments of up to $15.0 million through fiscal 2007 if certain technology and performance milestones are achieved. Additional information is provided in Note 3 of our Consolidated Financial Statements. In addition, in connection with the ISE acquisition, which occurred in November 2004, we are obligated to make additional cash payments of up to $20.0 million through fiscal 2007 if certain performance milestones are achieved. Additional information is provided in Note 13 of our Consolidated Financial Statements. The contingent consideration payments are not included in the table above.

        The expected timing of payment of the obligations discussed above is estimated based on current information. Timing of payment and actual amounts paid may be different depending on the time of

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receipt of goods or services or changes to agreed-upon amounts for some obligations. Amounts disclosed as contingent or milestone-based obligations are dependent on the achievement of the milestones or the occurrence of the contingent events and can vary significantly.

Stock Option Plans

        Under our 1992 Stock Option Plan (the 1992 Plan), 38,951,016 shares of common stock have been authorized for issuance. Pursuant to the 1992 Plan, the Board of Directors (the Board) may grant either incentive or non-qualified stock options to purchase shares of common stock to employees and consultants, excluding non-employee directors at not less than 100% of the fair market value of those shares on the grant date. Stock options granted under the 1992 Plan generally vest over a period of four years and expire ten years from the date of grant. As of October 31, 2004, 8,284,470 stock options remain outstanding and 7,128,810 shares of common stock are reserved for future grants under this plan.

        Under our 1998 Non-Statutory Stock Option Plan (the 1998 Plan), 53,247,068 shares of common stock have been authorized for issuance. Pursuant to the 1998 Plan, the Board may grant non-qualified stock options to employees and consultants, excluding executive officers and directors. Exercisability, option price and other terms are determined by the Board but the option price shall not be less than 100% of the fair market value of those shares on the grant date. Stock options granted under the 1998 Plan generally vest over a period of four years and expire seven to ten years from the date of grant. As of October 31, 2004, 26,150,004 stock options remain outstanding and 5,460,416 shares of common stock were reserved for future grants under this plan.

        Under our 1994 Non-Employee Directors Stock Option Plan (the Directors Plan), 2,100,000 shares were authorized for issuance. The Directors Plan provided for automatic grants to each non-employee member of the Board upon initial appointment or election to the Board, upon reelection and for annual service on Board committees. The option price was not less than 100% of the fair market value of those shares on the grant date. Under the Directors Plan, as originally adopted, new directors received an option for 40,000 shares, vesting in equal installments over four years. In addition, each continuing director who was elected at an annual meeting of stockholders received an option for 20,000 shares and an additional option for 10,000 shares for each Board committee membership, up to a maximum of two committee service grants per year. In August 2003, the Board amended the Directors Plan in order to reduce the size of the initial and committee grants to 30,000 and 5,000 shares, respectively. The annual and committee service option grants vest in full on the date immediately prior to the date of the annual meeting following their grant, assuming continued board or committee service through such date. In the case of directors appointed to the Board between annual meetings, the annual and any committee grants were prorated based upon the amount of time since the last annual meeting. The Directors Plan expired as to future grants in October 2004; as of October 31, 2004, 1,297,660 stock options remain outstanding. With the expiration of the Directors Plan, we expect to seek stockholder approval of a new plan for non-employee directors at our 2005 annual meeting of stockholders.

        We have assumed certain option plans in connection with acquisitions. Generally, the options granted under these plans have terms similar to our own options. The exercise prices of such options have been adjusted to reflect the relative exchange ratios. We do not intend to make future grants out of these option plans.

        We monitor dilution related to our option program by comparing net option grants in a given fiscal period to the number of shares outstanding. The dilution percentage is calculated as the new option grants for the fiscal period, net of options forfeited by employees leaving Synopsys, divided by the total outstanding shares at the end of such fiscal period. The option dilution percentages were 2.2% and 0.9% for fiscal 2004 and 2003, respectively.

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        A summary of the distribution and dilutive effect of options granted is as follows:

(1)

Total grants, net of returns and cancellations, include the cancellation of approximately 812,000 options from a former named executive officer. If these options had been included in the calculation, the net grants for fiscal 2003 as a percentage of outstanding shares would have been 1.4%.

(2)

Calculations based on named executive officers for each fiscal year.

        A summary of our option activity and related weighted-average exercise prices for fiscal 2004 is as follows:

(1)

Shares remaining available for grant under the Directors Plan on the date of expiration of such plan.

        For additional information regarding our stock option activity during fiscal 2004, please see Note 7 of our Notes to Consolidated Financial Statements in Part II, Item 8. Financial Statements and Supplementary Data.

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        A summary of outstanding in-the-money and out-of-the-money options and related weighted-average exercise prices as of October 31, 2004 is as follows:

(1)

Out-of-the-money options are those options with an exercise price equal to or above the closing price of $16.24 on October 29, 2004, the last trading day of fiscal 2004.

        The following table sets forth further information regarding individual grants of options during fiscal 2004 to the Chief Executive Officer and each of the other four most highly compensated executive officers (named executive officers) serving as such on October 31, 2004 whose compensation earned during fiscal 2004 exceeded $100,000. We refer to these individuals as named executive officers.