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UNITED STATES
SECURITIES AND EXCHANGE COMMISSION
Washington, D.C. 20549

FORM 10-K

Commission File Number: 000-18032

LATTICE SEMICONDUCTOR CORPORATION
(Exact name of Registrant as specified in its Charter)

Registrant's telephone number, including area code: (503) 268-8000

Securities registered pursuant to Section 12(b) of the Act: None
Securities registered pursuant to Section 12(g) of the Act:

Title of Class

Common Stock, $.01 par value

        Indicate by check mark whether the Registrant (1) has filed all reports required to be filed by Section 13 or 15(d) of the Securities Exchange Act of 1934 during the preceding 12 months (or for such shorter period that the Registrant was required to file such reports), and (2) has been subject to such filing requirements for the past 90 days. Yes  ý    No  o

        Indicate by check mark if disclosure of delinquent filers pursuant to Item 405 of Regulation S-K is not contained herein, and will not be contained, to the best of the Registrant's knowledge, in definitive proxy or information statements incorporated by reference in Part III of this Form 10-K or any amendment to this Form 10-K. ý

        Indicate by check mark whether the Registrant is an accelerated filer (as defined in Rule 12b-2 of the Act). Yes  ý    No  o

        As of June 27, 2003 (the last business day of the Registrant's second quarter of fiscal 2003), the aggregate market value of the shares of voting stock (Common Stock) of the Registrant held by non-affiliates was approximately $632.9 million based on the last sales price of the Registrant's Common Stock on the Nasdaq National Market on such date. Shares of Common Stock held by each officer and director and by each person who owns 5% or more of the outstanding Common Stock have been excluded in that such persons may be deemed affiliates. This determination of affiliate status is not necessarily a conclusive determination for other purposes.

        As of March 29, 2004, 113,115,442 shares of the Registrant's common stock were outstanding.

DOCUMENTS INCORPORATED BY REFERENCE

        Portions of the definitive proxy statement of the Registrant to be filed pursuant to Regulation 14A for the 2004 Annual Meeting of Stockholders to be held on May 11, 2004 are incorporated by reference in Part III hereof.

LATTICE SEMICONDUCTOR CORPORATION
FORM 10-K
ANNUAL REPORT
TABLE OF CONTENTS

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Forward-Looking Statements

        This Annual Report on Form 10-K contains forward-looking statements within the meaning of Section 27A of the Securities Act of 1933, as amended, and Section 21E of the Exchange Act. Any statements about our expectations, beliefs, plans, objectives, assumptions or future events or performance are not historical facts and may be forward-looking. We use words or phrases such as "anticipates," "believes," "estimates," "expects," "intends," "plans," "projects," "may," "will," "should," "continue," "ongoing," "future," "potential" and similar words or phrases to identify forward-looking statements.

        Forward-looking statements involve estimates, assumptions, risks and uncertainties that could cause actual results to differ materially from those expressed in them. Among the key factors that could cause our actual results to differ materially from the forward-looking statements are delay in product or technology development, change in economic conditions of the various markets we serve, lack of market acceptance or demand for our new products, dependencies on silicon wafer suppliers and semiconductor assemblers, the impact of competitive products and pricing, opportunities or acquisitions that we pursue, the availability and terms of financing, and the other risks that are described herein and that are otherwise described from time to time in our filings with the Securities and Exchange Commission, including but not limited to the items discussed in "Factors Affecting Future Results" set forth in "Management's Discussion and Analysis of Financial Condition and Results of Operations" in Item 7 of this report. You should not unduly rely on forward-looking statements because our actual results could differ materially from those expressed in any forward-looking statements made by us. Further, any forward-looking statement applies only as of the date on which it is made. We are not required to update any forward-looking statement or statements to reflect events or circumstances after the date on which such statement is made or to reflect the occurrence of unanticipated events.

Item 1. Business.

        Lattice Semiconductor Corporation designs, develops and markets high performance programmable logic devices, or PLDs, and related software. Programmable logic devices are widely-used semiconductor components that can be configured by end customers as specific logic circuits, and thus enable shorter design cycle times and reduced development costs. Our end customers are primarily original equipment manufacturers in the communications, computing, industrial, automotive, medical, consumer and military end markets.

        Lattice was incorporated in Oregon in 1983 and reincorporated in Delaware in 1985. Our principal offices are located at 5555 N.E. Moore Court, Hillsboro, Oregon 97124, our telephone number is (503) 268-8000 and our website can be accessed at www.latticesemi.com. Information contained or referenced on our website is not incorporated by reference and does not form a part of this Annual Report on Form 10-K.

        We report based on a 52 or 53 week year ending on the Saturday closest to December 31. For ease of presentation, we have adopted the convention of using March 31, June 30, September 30 and December 31 as period end dates for all financial statement information. Our 2003 fiscal year was a 53-week year.

PLD Market Background

        Three principal types of digital integrated circuits are used in most electronic systems: microprocessors, memory and logic. Microprocessors are used for control and computing tasks, memory is used to store programming instructions and data, and logic is employed to manage the interchange and manipulation of digital signals within a system. Logic contains interconnected groupings of simple logical "and" and logical "or" functions, commonly described as "gates." Typically, complex combinations of individual gates are required to implement the specialized logic functions required for

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systems applications. While system designers use a relatively small variety of standard products to meet their microprocessor and memory needs, they require a wide variety of logic products in order to achieve end product functionality and differentiation.

        Logic circuits are found in a wide range of today's digital electronic equipment including communications, computing, industrial, automotive, medical, consumer and military systems. According to World Semiconductor Trade Statistics ("WSTS"), a semiconductor industry association, logic accounted for approximately 26% of the estimated $140 billion worldwide digital integrated circuit market in 2003. The logic market encompasses, among other segments, standard logic, custom-designed application specific integrated circuits, or ASICs, which include conventional gate-arrays, standard cells and full custom logic circuits, and PLDs.

        Manufacturers of electronic equipment are challenged to bring differentiated products to market quickly. These competitive pressures often preclude the use of custom-designed ASICs, which generally entail significant design risks, non-recurring costs and time delays. Standard logic products, an alternative to custom-designed ASICs, limit a manufacturer's flexibility to adequately customize an end system. PLDs address this inherent dilemma. PLDs are standard products, purchased by systems manufacturers in a "blank" state, that can be custom configured into a virtually unlimited number of specific logic functions by programming the device with electrical signals. PLDs give system designers the ability to quickly create custom logic functions to provide product differentiation without sacrificing rapid time to market. Certain PLD products, including our own, are reprogrammable, meaning that the logic configuration can be modified, if needed, after the initial programming. ISP™ and XP™ PLDs, pioneered by us, extend the flexibility of standard reprogrammable PLDs by allowing the system designer to configure and reconfigure logic functions using system power supplies and without removing the PLD from the system board.

        According to WSTS, the PLD market was approximately $2.7 billion in 2003. Within this market there are two main segments, complex PLD ("CPLD") and field programmable gate array ("FPGA"), each representing a distinct silicon architectural approach. In 2003, CPLD was a $0.5 billion market while FPGA was a $2.0 billion market.

        Products based on the two alternative PLD architectures are generally optimal for different types of logic functions, although many logic functions can be implemented using either architecture. CPLDs are characterized by a regular building block structure of wide-input logic cells, called macrocells, and use of a centralized logic interconnect scheme. FPGAs are characterized by a narrow-input logic cell and use a distributed interconnect scheme. FPGAs may also contain dedicated blocks of fixed circuits such as memory, high-speed interface logic or processing engines. Although CPLDs and FPGAs are typically suited for use in distinct types of logic applications, we believe that a substantial portion of PLD customers utilize both CPLD and FPGA architectures within a single system design, partitioning logic functions across multiple devices to optimize overall system performance and cost.

Technology

        We believe that our proprietary E²CMOS® technology is the preferred process technology for CPLD products due to its inherent performance, reprogrammability and testability benefits. E²CMOS technology, through its fundamental ability to be programmed and erased electronically, serves as the foundation for our ISP and XP products.

        We pioneered the development of in-system programmability ("ISP™"), which has become an industry standard feature in the PLD market. Our ISP devices can be configured and reconfigured by a system designer without being removed from the printed circuit board. These ISP devices can allow customers to reduce design cycle times, accelerate time to market, reduce prototyping costs, reduce manufacturing costs and lower inventory requirements. Our ISP devices can also provide customers the

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opportunity to perform simplified and cost-effective field reconfiguration through a data file transferred by computer disk or serial data signal.

        In 2002, we introduced XP, or extended programmability, technology. Traditional PLDs have been based on either volatile SRAM technology, which is infinitely reconfigurable, or non-volatile E²CMOS technology, which is reprogrammable but not infinitely reconfigurable. Both these technologies require compromises on the part of the customer. XP technology, based on an embedded flash process, is the only programming technology that enables a programmable logic device to be both non-volatile and infinitely reconfigurable.

Products

        We strive to offer innovative and differentiated programmable solutions based on our proprietary technology.

CPLD Products

        Since 1992, we have focused on developing a leadership portfolio of CPLD products and increasing the percentage of our overall revenue derived from this attractive market. During 2003, approximately 69% of our revenue was derived from CPLD products, as compared to 69% in 2002 and 76% in 2001. At present, we offer the industry's broadest line of CPLDs based on our numerous families of ispLSI® and ispMACH® products. In the future, we plan to continue to introduce new families of innovative CPLD products, as well as improve the performance and reduce the manufacturing cost of our existing product families based on market needs.

        Our newest CPLD product families use innovative architectures and are targeted towards the low voltage portion of the market. We believe that our multiple families of leadership CPLD products provide us a competitive advantage in this market. The key features of these families are described in the table below:

        In addition to high performance, the ispMACH 4000Z family features a new architecture optimized to ensure ultra-low power consumption. Devices within this new family, targeted toward handheld and portable equipment, typically operate using 10-15 microamps of current while in standby mode.

FPGA Products

        In 2002, we entered the FPGA market as a result of our acquisition of the FPGA business of Agere and the introduction of an internally developed product family. During 2003, approximately 18% of our revenue was derived from FPGA products, as compared to 12% in 2002 and 0% in 2001. At present we offer the FPGA product families described below. In the future, we plan to introduce new

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families of innovative, high performance and higher density FPGAs. Key features of our ORCA FPGA families are described in the table below:

        In addition, we offer a family of field programmable system chips ("FPSC"). FPSCs, which combine generic FPGAs with embedded intellectual property cores on a single programmable chip, offer customers the ability to quickly implement complex system-level designs in a flexible manner. Currently, we offer seven FPSC devices, the ORT82G5, ORT42G5, ORT8850L, ORT8850H, ORLI10G, ORSO82G5 and ORSPI4, based on the ORCA 4 FPGA platform. These devices incorporate high-speed interface protocols, offering up to 4.25 Gbs SERDES, and other application-specific circuit blocks that allow customers to develop high performance designs to implement 10 Gigabit ethernet and SONET applications within advanced communications systems.

        During 2002, we introduced two new FPGA product families utilizing our innovative XP, or extended programmability technology. The ispXPLD family, based on a hybrid architecture, combines the benefits of a wide-input CPLD logic cell with the availability of abundant memory resources. Offering up to 1024 logic macrocells, propagation delays as low as 4 nanoseconds and up to 512 Kb of memory, the ispXPLD offers customers a new alternative for high density logic designs. The ispXPGA family, based on a mainstream FPGA architecture, offers densities of up to 1.25 million logic gates and brings the benefits of XP technology to the FPGA marketplace.

        We also offer an additional FPGA product family, ispGDX, that targets a unique aspect of the programmable logic market. This family extends in-system programmability to the circuit board level using an innovative digital cross-point switch architecture. Offered with propagation delays as low as 3.0 nanoseconds, up to 256 input/output pins and complete pin-to-pin signal routing, ispGDX products are targeted towards digital signal interconnect and interface applications.

Other Products

        We also offer programmable analog and mixed signal products as we believe these devices provide an opportunity to extend our proprietary technology to an untapped potential market. The innovative architecture of our ispPAC® products allows designers to quickly and easily program resistor and capacitor values, gain and signal polarity and circuit interconnect to implement a wide variety of functions. Our ispPAC products are targeted towards power management, filtering and signal conditioning applications and can replace numerous discrete analog components. ispPAC designs are implemented and programmed via a personal computer using our software development tool, PAC-Designer®.

Software Development Tools

        All of our products are supported by our ispLEVER™ 3.1 software development tool suite. This latest version of ispLEVER software supports all of our CPLD and FPGA product families. Supporting both the PC and UNIX platforms, ispLEVER allows our customers to enter, verify and synthesize a design, perform logic simulation and timing analysis, assign input/output pins, designate critical paths, debug, execute automatic timing-driven place and route tasks and download a program to one of our ISP devices. Seamlessly integrated with third-party electronic design automation environments, ispLEVER provides a front-to-back design flow that leverages a customer's prior investment in tools offered by Aldec, Cadence, Mentor Graphics, Synopsys and Synplicity. In the future, we plan to continue to enhance and expand the capability of our software development tool suite.

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        We also provide a variety of software algorithms that support in-system programming of our ISP devices through an interface cable or directly from a system microprocessor.

Low Density PLD Products—SPLD

        We offer the industry's broadest line of low-density CMOS PLDs, or SPLDs, based on our 18 families of GAL® products offered in over 200 speed, power, package and temperature range combinations. These devices range in complexity from approximately 200 to 1,000 logic gates and are typically assembled in 20-, 24- and 28-pin standard dual in-line packages and in 20- and 28-pin standard plastic leaded chip carrier packages. We offer the standard 16V8, 20V8 and 22V10 architectures in a variety of speed grades, with propagation delays as low as 3.5 nanoseconds, the highest performance in the industry. In addition, we offer several proprietary extension architectures, the isp22V10, 6001/2, 16VP8, 16V8Z, 18V10, 20VP8, 20V8Z, 20RA10, 20XV10 and 26V12, each of which is optimized for specific applications. We also offer a full range of 3.3-volt standard architectures, the isp22LV10, 16LV8, 20LV8, 22LV10 and 26CLV12, in a variety of speed grades, with propagation delays as low as 3.5 nanoseconds, the highest performance in the industry. During 2003, approximately 13% of our revenue was derived from SPLD products, as compared to 19% in 2002 and 24% in 2001.

Product Development

        We place substantial emphasis on new product development and believe that continued investment in this area is required to maintain our competitive position. Our product development activities emphasize new proprietary products, enhancement of existing products and process technologies and improvement of software development tools. Product development activities occur in Hillsboro, Oregon; San Jose, California; Broomfield, Colorado; Naperville, Illinois; Bethlehem, Pennsylvania; Austin, Texas; Salt Lake City, Utah; Shanghai, China; and Corsham, England.

        Research and development expenses were $71.7 million in 2001, $85.8 million in 2002 and $87.1 in 2003. We expect to continue to make significant future investments in research and development.

Operations

        We do not manufacture our own silicon wafers. We maintain strategic relationships with large semiconductor foundries to source our finished silicon wafers. This strategy allows us to focus our internal resources on product, process and market development, and eliminates the fixed cost of owning and operating manufacturing facilities. We are also able to take advantage of the ongoing advanced process technology development efforts of semiconductor foundries. In addition, all of our assembly operations and most of our test operations are performed by outside suppliers. We perform certain test operations and reliability and quality assurance processes internally. We have achieved an ISO 9001 quality certification, which is an indication of our high internal operational standards.

Wafer Fabrication

        We source silicon wafers from our foundry partners, Seiko Epson in Japan, United Microelectronics Corporation ("UMC") in Taiwan and Chartered Semiconductor Manufacturing, Ltd. ("Chartered Semiconductor") in Singapore, pursuant to agreements with each company and their respective affiliates. We negotiate wafer volumes, prices and other terms with our foundry partners and their respective affiliates on a periodic basis.

        In March 2004 we announced that we will also be sourcing wafers on advanced process technologies from Fujitsu Limited in Japan.

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Assembly

        After wafer fabrication and initial testing, we ship wafers to independent subcontractors for assembly. During assembly, wafers are separated into individual die and encapsulated in plastic or ceramic packages. Presently, we have qualified long-term assembly partners in China, Malaysia, the Philippines, South Korea, and Taiwan.

Testing

        We electrically test the die on each wafer prior to shipment for assembly. Following assembly, prior to customer shipment, each product undergoes final testing and quality assurance procedures. Final testing on certain products is performed by independent contractors in China, Malaysia, the Philippines, South Korea and Taiwan, and at our Oregon facility.

Marketing, Sales and Customers

        We sell our products directly to end customers through a network of independent manufacturers' representatives and indirectly through a network of independent distributors. We also employ a direct sales management and field applications engineering organization to support our end customers and indirect sales resources. Our end customers are primarily original equipment manufacturers in the communications, computing, industrial, automotive, medical, consumer and military end markets.

        As of December 2003, we used 18 manufacturers' representatives and two distributors, Arrow Electronics, Inc. and Avnet Inc., in North America. We have also established export sales channels in over 30 foreign countries through a network of over 30 sales representatives and distributors. Approximately two-thirds of our North American sales and the majority of our export sales are made through distributors.

        We protect each of our North American distributors and some of our foreign distributors against reductions in published prices, and expect to continue this policy in the foreseeable future. We also allow returns from these distributors of unsold products under certain conditions. For these reasons, we do not recognize revenue until products are resold by these distributors to an end customer.

        We provide technical and marketing support to our end customers with engineering staff based at our headquarters, product development centers and selected field sales offices. We maintain numerous domestic and international field sales offices in major metropolitan areas.

        Export sales as a percentage of our total revenue were 54% in 2001, 60% in 2002 and 68% in 2003. Both export and domestic sales are denominated in U.S. dollars, with the exception of sales to Japan, which are denominated in yen. If our export sales decline significantly there would be a material adverse impact on our business and results of operations.

        Our products are sold to a large and diverse group of customers. No individual end customer accounted for more than 10% of total revenue in 2001, 2002 or 2003. No export sales to any given country accounted for more than 10% of total revenue in 2001 or 2002. Export sales to Japan were approximately 11% of revenue in 2003, while export sales to China and Taiwan were each slightly less than 10%.

Backlog

        Our backlog of scheduled and released orders as of December 31, 2003 was approximately $45.1 million as compared to approximately $37.2 million as of December 31, 2002. This backlog consists of direct customer and distributor orders scheduled for delivery within the next 90 days. Distributor orders accounted for the majority of the backlog in both periods. Direct customer orders may be changed, rescheduled or cancelled under certain circumstances without penalty prior to

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shipment. Additionally, distributor orders generally may be changed, rescheduled or cancelled without penalty prior to shipment. Furthermore, distributor shipments are subject to rights of return and price adjustment. Revenue associated with distributor shipments is not recognized until the product is resold to an end customer. Typically, the majority of our revenue results from orders placed and filled within the same period. Such orders are referred to as "turns orders." By definition, turns orders are not captured in a backlog measurement made at the beginning of a period. We do not anticipate a significant change in this business pattern. For all these reasons, backlog as of any particular date should not be used as a predictor of revenue for any future period.

Competition

        The semiconductor industry is intensely competitive and characterized by rapid rates of technological change, product obsolescence and price erosion. Our current and potential competitors include a broad range of semiconductor companies from emerging companies to large, established companies, many of which have greater financial, technical, manufacturing, marketing and sales resources than we do.

        The principal competitive factors in the PLD market include product features, price, customer support, and sales, marketing and distribution strength. The availability of competitive software development tools is also critical. In addition to product features such as density, speed, power consumption, reprogrammability, design flexibility and reliability, competition in the PLD market occurs on the basis of price and market acceptance of specific products and technology. We believe that we compete favorably with respect to each of these factors. We intend to continue to address these competitive factors by working to continually introduce product enhancements and new products, by seeking to establish our products as industry standards in their respective markets, and by working to reduce the manufacturing cost of our products.

        In the PLD market, we directly compete with Actel Corporation, Altera Corporation and Xilinx Inc., all of whom offer competing products. We also indirectly compete with other semiconductor companies who provide non-PLD based logic solutions. Although to date we have not experienced significant competition from companies located outside the United States, such companies may become a more significant competitive factor in the future. Competition may also increase if other semiconductor companies seek to expand into our market. Any such increases in competition could have a material adverse effect on our operating results.

Patents

        We seek to protect our products and wafer fabrication process technologies primarily through patents, trade secrecy measures, copyrights, mask work protection, trademark registrations, licensing restrictions, confidentiality agreements and other approaches designed to protect proprietary information. There can be no assurance that others may not independently develop competitive technology not covered by our intellectual property rights or that measures we take to protect our technology will be effective.

        We hold numerous domestic, European and Asian patents and have patent applications pending in the United States, Asia and Europe. Our current patents will expire at various times between 2004 and 2022. There can be no assurance that pending patent applications or other applications that may be filed will result in issued patents, or that any issued patents will survive challenges to their validity. Although we believe that our patents have value, there can be no assurance that our patents, or any additional patents that may be issued in the future, will provide meaningful protection from competition. We believe that our success will depend primarily upon the technical expertise, experience, creativity and the sales and marketing abilities of our personnel.

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        Patent and other proprietary rights infringement claims are common in our industry. There can be no assurance that, with respect to any claim made against us, we could obtain a license on terms or under conditions that would not harm our business.

Licenses and Agreements

Advanced Micro Devices

        In 1999, as part of our acquisition of Vantis Corporation, a wholly-owned subsidiary of Advanced Micro Devices, Inc. ("AMD"), we entered into an agreement with AMD pursuant to which we have cross-licensed Vantis patents with AMD patents, having an effective filing date on or before June 15, 1999, related to PLD products. This cross-license was made on a worldwide, non-exclusive and royalty-free basis.

        Additionally, as part of our acquisition of Vantis, we acquired certain third-party license rights held by Vantis prior to the acquisition. Included are rights to use certain Xilinx patents to manufacture, market and sell products.

Agere Systems

        In 2002, as part of our acquisition of the FPGA business of Agere, we entered into an intellectual property agreement with Agere and Agere Systems Guardian Corporation. Pursuant to this agreement, these Agere companies assigned or licensed to us certain FPGA and FPSC patents, trademarks, software and other intellectual property rights and technology, and we licensed back rights in these same assets. These cross-licenses were made on a worldwide and royalty-free basis.

Altera

        In 2001, we entered into a comprehensive, royalty-free patent cross-license agreement and a multi-year patent peace agreement with Altera.

Chartered Semiconductor

        In 2002, in order to support our acquired and subsequently developed ORCA FPGA products, Chartered Semiconductor and its affiliates agreed to provide us with manufactured wafers in quantities based on six-month rolling forecasts. We have agreed to make a portion of the rolling forecasts non-cancellable. Prices for the wafers obtained are reviewed and adjusted periodically. Wafers for our products are manufactured at the facilities of Chartered and its affiliates in Singapore.

Fujitsu

        In March 2004, we announced that Fujitsu Limited has agreed to manufacture our next generation FPGA products on its 130 nanometer and 90 nanometer CMOS process technologies, as well as on a 130 nanometer technology with embedded Flash memory that we are jointly developing with Fujitsu. Additionally, in an effort to secure a long-term, stable advanced technology wafer supply, we plan to invest between $100 million and $200 million in Fujitsu's planned new 300mm wafer fab. Presently, we contemplate making this investment in stages before the end of 2005 and structuring the investment as an advance payment for production wafers and for access to future process technologies. The detailed terms of the investment are not yet finalized.

Seiko Epson/Epson Electronics America

        Epson Electronics America ("EEA"), an affiliated U.S. distributor of Seiko Epson, has agreed to provide us with manufactured wafers in quantities based on six-month rolling forecasts. We have agreed to make a portion of the rolling forecasts non-cancellable. Prices for the wafers obtained from EEA are

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reviewed and adjusted periodically. Wafers for our products are manufactured in Japan at Seiko Epson's wafer fabrication facilities and are delivered to us by EEA.

        In 1997, and as subsequently amended in January 2002, we entered into an advance production payment agreement with Seiko Epson and EEA under which we agreed to advance up to approximately $69 million, payable upon completion of specific milestones, to Seiko Epson to finance construction of an eight-inch sub-micron semiconductor wafer manufacturing facility. The timing of the payments is related to certain milestones in the development of the facility. Under the terms of the agreement, the advance is to be repaid with semiconductor wafers over a multi-year period. The agreement calls for wafers to be supplied by Seiko Epson through EEA pursuant to purchase agreements concluded with EEA. Payments of approximately $51.3 million have been made under this agreement. Cumulatively, approximately $15.6 million of these payments have been repaid to us in the form of semiconductor wafers. We do not anticipate making additional payments under this agreement.

UMC Group

        Beginning in 1995, we entered into a series of agreements with UMC pursuant to which we agreed to make several equity investments in entities now directly owned by UMC. Under the terms of these agreements, we invested approximately $68.5 million for the right to purchase a percentage of UMC's wafer production at market prices.

        As of December 31, 2003, we owned 91.7 million shares of UMC of which 23.3 million were restricted from sale for more than one year by the terms of our agreements with UMC. Under the terms of our agreements, if we sell any of these restricted shares, our rights to guaranteed wafer capacity at UMC may be reduced on a pro-rata basis based on the number of shares that we sell. If we sell over 10.1 million of these restricted shares, we may lose all of our rights to guaranteed wafer capacity at UMC.

        In the first quarter of 2004, we sold 10.0 million of our unrestricted UMC shares for approximately $9.2 million in cash, resulting in a gain of approximately $2.5 million. This gain will be reflected in Other Income, net, in our consolidated financial statements for the quarter ended March 31, 2004.

Employees

        As of December 31, 2003 we had 1,048 full-time employees. We believe that our future success will depend, in part, on our ability to continue to attract and retain highly skilled technical and management personnel. None of our employees is subject to a collective bargaining agreement. We have never experienced a work stoppage and consider our employee relations to be good.

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EXECUTIVE OFFICERS AND DIRECTORS OF THE REGISTRANT

        The following individuals currently serve as our executive officers and directors:

        Cyrus Y. Tsui joined Lattice in September 1988 as President and Chief Executive Officer and in March 1991 was named Chairman of the Board. From 1987 until he joined Lattice, Mr. Tsui was Corporate Vice President and General Manager of the Programmable Logic Division of AMD. He was Vice President and General Manager of the Commercial Products Divisions of Monolithic Memories Incorporated (MMI) from 1983 until its merger with AMD in 1987. Mr. Tsui has held technical and managerial positions in the semiconductor industry for over 30 years and worked in the programmable logic industry since its inception.

        Stephen A. Skaggs joined Lattice in December 1992 as Director, Corporate Development. He was elected Senior Vice President, Chief Financial Officer and Secretary in August 1996. In October 2003 he was elected President.

        Jan Johannessen rejoined Lattice in October 2001 as Vice President, Investments. In October 2003, he was elected Corporate Vice President and Chief Financial Officer. He originally joined Lattice in 1983 and served as Vice President and Chief Financial Officer between 1987 and 1993. From 1993 to 2001 he worked as an independent venture capitalist.

        Frank J. Barone joined Lattice in June 1999 as a Corporate Vice President as a result of our Vantis acquisition. From September 1997 until he joined our company, Mr. Barone was Chief Operating Officer of Vantis. Prior thereto, Mr. Barone held various technical and managerial positions at AMD. He has worked in the programmable logic industry since 1978.

        Stephen M. Donovan joined Lattice in October 1989 and has served as Director of Marketing and Director of International Sales. He was elected Vice President, International Sales in August 1993. He was promoted to Corporate Vice President, Sales, in May 1998. Mr. Donovan has worked in the programmable logic industry since 1982.

        Jonathan K. Yu joined Lattice in February 1992 as Vice President, Operations. He was elected Corporate Vice President, Business Development in August 1996. Mr. Yu has held technical and managerial positions in the semiconductor industry for over 30 years.

        Martin R. Baker joined Lattice in January 1997 as Vice President and General Counsel. From 1991 until he joined Lattice, Mr. Baker held legal positions with Altera Corporation.

        Rodney F. Sloss joined Lattice in May 1994 as Vice President, Finance.

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        Mark O. Hatfield has been a member of our board of directors since 1997. Mr. Hatfield is a former U.S. Senator from Oregon, a position he held until January 1997. He has served as a Distinguished Professor at Portland State University since 1997, a Distinguished Professor at George Fox University since 1997 and an Adjunct Professor at Lewis & Clark College since 2000.

        Daniel S. Hauer has been a member of our board of directors since 1987. Mr. Hauer served as the Chairman of the Board and Chief Executive Officer of Epson Electronics America until November 1998. Since that time, Mr. Hauer has worked as a business consultant.

        Soo Boon Koh joined our board of directors in August 2000. Ms. Koh has served as Managing Partner of iGlobe Partners Fund, L.P., a venture capital firm located in Singapore and the United States, since October 1999. She previously served as Sr. Vice President and Deputy General Manager of Vertex Management Pte, Ltd. until June 1999.

        Harry A. Merlo was a founding member of our board of directors in 1983. Mr. Merlo has been the President of Merlo Corporation since July 1995. He previously served as the founding President and Chairman of the Board of Louisiana-Pacific Corporation until June 1995.

        Larry W. Sonsini has been a member of our board of directors since 1991. Mr. Sonsini is a member of Wilson Sonsini Goodrich & Rosati, Professional Corporation, a law firm, and Chairman of the firm's Executive Management Committee. He also serves on the board of directors of Brocade Communications Systems, Inc., Echelon Corporation, LSI Logic Corporation, Pixar, Inc. and Silicon Valley Bancshares.

Available Information

        We make available free of charge through our website at www.latticesemi.com, via a link to the SEC's website at www.sec.gov, our annual reports on Form 10-K, quarterly reports on Form 10-Q and current reports on Form 8-K and amendments to those reports as soon as reasonably practicable after such materials are electronically filed with, or furnished to, the SEC. You may also obtain free copies of these materials by contacting our Investor Relations Department at 5555 N.E. Moore Court, Hillsboro, Oregon 97124-6421, telephone (503) 268-8000.

Item 2. Properties.

        Our corporate headquarters consists of land and 200,000 square feet of buildings we own in Hillsboro, Oregon. We also own two research and development facilities totaling 29,000 square feet and approximately 6,000 square feet of dormitory facilities in Shanghai, China. We lease a 133,000 square foot research and development facility in San Jose, California through 2008; a 25,000 square foot research and development facility in Austin, Texas through 2011; and a 7,500 square foot research and development facility in the United Kingdom through 2013. We also lease, on a short-term basis, research and development facilities in Colorado, Illinois, Pennsylvania and Utah, and office facilities in multiple metropolitan locations for our domestic and international sales staff. Additionally, we lease (through 2006) an 80,000 square foot facility in Sunnyvale, California which has been subleased to a third party through the end of the lease term. We believe that our existing facilities are adequate for our current and foreseeable future needs.

Item 3. Legal Proceedings.

        We are not currently a party to any material legal proceedings.

Item 4. Submission of Matters to a Vote of Security Holders.

        Not applicable.

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PART II

Item 5. Market for the Registrant's Common Stock and Related Stockholder Matters.

        Our common stock is traded on the over-the-counter market and prices are quoted on the Nasdaq National Market under the symbol "LSCC." The following table sets forth the low and high sale prices for our common stock for the last two fiscal years, as reported by the Nasdaq National Market. As of March 29, 2004, we had approximately 484 stockholders of record.

        The payment of dividends on our common stock is within the discretion of our Board of Directors. We intend to retain earnings to finance the growth of our business. We have never paid cash dividends.

Recent Sales of Unregistered Securities

        On May 6, 2003, we issued a warrant to purchase 256,661 shares of our common stock to Bain & Company, Inc., in connection with consulting services provided to us. The warrant has an exercise price of $9.05 per share, and vests at a rate of 21,388.42 shares on the first day of each month, beginning March 1, 2003, subject to Bain's continued service as a consultant to us. The foregoing transaction was exempt from registration under the Securities Act of 1933, as amended, pursuant to Section 4(2) thereof.

        On June 20, 2003, we sold $200 million in principal amount of our Zero Coupon Convertible Subordinated Notes due July 1, 2010 to Goldman Sachs & Co., the initial purchaser, for $195.0 million pursuant to the exemption from registration under Section 4(2) of the Securities Act of 1933, as amended, for resale by the initial purchaser to qualified institutional buyers pursuant to Rule 144A under the Securities Act of 1933, as amended. Holders of these notes may convert the notes into shares of our common stock at any time before the close of business on the date of their maturity, unless the notes have been previously redeemed or repurchased, if (1) the price of our common stock issuable upon conversion of a note reaches a specified threshold, (2) the notes are called for redemption, (3) specified corporate transactions occur or (4) the trading price of the notes falls below certain thresholds. The conversion price is approximately $12.06 per share, subject to adjustment in certain circumstances. On or after July 1, 2008, we have the option to redeem all or a portion of the notes that have not been previously repurchased or converted at 100% of the principal amount of the notes. On July 1, 2008, holders have the option to require us to purchase all or a portion of their notes in cash at 100% of the principal amount of the notes. Holders also have the right, subject to certain conditions, to require us to repurchase the notes in the event of a "fundamental change" (as defined in the indenture governing the notes) at 100% of the principal amount of the notes.

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Item 6. Selected Financial Data.

(1)

Includes $5,745, $2,962 and $397 of amortization of deferred stock compensation expense for the years ended December 31, 2003, December 31, 2002 and December 31, 2001, respectively, attributable to research and development activities.

        All share and per share amounts have been adjusted retroactively to reflect two-for-one stock splits effected in the form of stock dividends and paid on October 11, 2000 and September 16, 1999.

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Unaudited Quarterly Data

(1)

In January 2004, management learned of certain incorrect accounting entries relating to our deferred income accounting for sales to distributors in the quarters ended June 30, 2003 and September 30, 2003. Pursuant to our accounting principles for revenue recognition, we defer reporting revenue from sales to distributors until the period in which the distributors resell our product to their customers. The Audit Committee of our Board of Directors undertook an investigation of this matter with the assistance of our independent auditor and outside legal counsel. That investigation is complete and the Audit Committee has recommended the adoption of certain internal control and system enhancements. We are currently implementing these Audit Committee directives. As a result of the investigation, we have determined that entries made in the second and third quarters of 2003 which reduced Accrued Expenses in the amount of $1.3 million and $4.2 million, respectively, were inappropriate. We also determined that our systems, procedures and controls surrounding (1) our estimation of resales by our distributors and (2) our determination of deferred revenue related to distributor inventories needed to be improved. During the investigation, we carried out additional procedures to (1) refine our estimate of the amount of distributor resale revenue and (2) refine our method for estimating deferred revenue related to distributor inventories. As a result of those additional procedures, we believe our Consolidated Balance Sheet Deferred Income account was understated at March 31, 2003, June 30, 2003 and September 30, 2003 by amounts requiring an adjustment of approximately $1.0 million, $1.6 million and $8.0 million, respectively to reduce Revenues previously recognized and approximately $0.2 million, $0.3 million and $1.3 million, respectively, to reduce Cost of Products Sold previously recognized. As previously noted, approximately $1.3 million and $4.2 million of the resulting adjustments to the Deferred Income account were incorrectly restored to the Deferred Income account in our June 30, 2003 and September 30, 2003 balance sheet, respectively, through an entry to Accrued Expenses instead of the Consolidated Statement of Operations. The Deferred Income account balance fell below the minimum required level to support inventory on distributors shelves primarily due to (1) non recurring transactions in the September 30, 2003 quarter related to distributor price adjustments and incorrect distributor reporting of resales in previously reported quarterly financial statements, and (2) over-estimates of revenue related to resales occurring in the current fiscal year. We have already implemented certain of the internal control and systems enhancements recommended by the Audit Committee and are currently implementing other Audit Committee directives that resulted from its investigation.

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Item 7. Management's Discussion and Analysis of Financial Condition and Results of Operations.

        Lattice Semiconductor Corporation designs, develops and markets high performance programmable logic devices, or PLDs, and related software. Programmable logic devices are widely-used semiconductor components that can be configured by the end customer as specific logic circuits, and enable the end customer to shorten design cycle times and reduce development costs. Our end customers are primarily original equipment manufacturers in the communications, computing, industrial, automotive, medical, consumer and military end markets.

Restatement and Change in Accounting Estimate During 2003

        We restated our Deferred Income and Accrued Expense Balance Sheet accounts, and Revenue and Cost of Products Sold accounts in the Consolidated Statement of Operations for the June and September quarters of 2003 and our Deferred Income, Revenue and Cost of Products Sold accounts for the March quarter of 2003 to correct accounting errors and to reflect a change in accounting estimate related to Deferred Income. For the 2003 year, the aforementioned restatement related to accrued expenses and the changes in accounting estimate reduced revenue by approximately $10.6 million, reduced cost of products sold by approximately $1.8 million, reduced gross margin by approximately $8.9 million and increased deferred income by approximately $8.9 million. The related circumstances are described in more detail in Note 1 to the table of Unaudited Quarterly Data in Item 6 of this Annual Report on Form 10-K.

Overview of 2003

        Revenue for our business in 2003 declined to approximately $210 million as compared to approximately $229 million in 2002 primarily due to continued weakness in the sales of our CPLD and SPLD products. Revenue from our FPGA products, on the other hand, grew from approximately $28 million in 2002 to $37 million in 2003. However, we saw an improvement in business conditions in the fourth quarter of 2003 which has continued during the first quarter of 2004 attributable to general strengthening in the PLD market and improvement in the communications end market. Future revenue growth is dependent, among other things, upon market acceptance of our new FPGA products.

        Our gross margin declined in 2003 to 57% from 60% in 2002 due to factors including distributor sales allowances, and to a lesser extent, lower production yields and average selling prices on our new products.

        Research and development expenses increased to approximately $87 million (41% of revenue) in 2003 compared to approximately $86 million in 2002 (38% of revenue). The majority of research and development spending is related to the continued development of next generation FPGA products. We expect research and development spending to continue at present levels during 2004 as we introduce our next generation FPGA products.

        Selling, general and administrative expenses were approximately $51 million in 2003 (24% of revenue) as compared to approximately $48 million in 2002 (21% of revenue) primarily due to marketing expenses related to new products and increased professional fees including those related to the restatement of the first, second and third quarter 2003 financial statements. To the extent our revenues continue to grow, we expect that there will be a less than proportionate increase in our selling, general and administrative expenses.

        Amortization of intangible assets of approximately $77 million in 2003 will decline by approximately $13 million per quarter beginning with the September quarter of 2004 as amortization of intangible assets acquired in the Vantis acquisition will be completed.

        Interest and other income (expense) of approximately $(3 million) in 2003 is primarily attributable to the issuance of Zero Coupon Convertible Subordinated Notes due July 1, 2010 and retirement of

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our 4³/4% Convertible Subordinated Notes due 2006 during the second and third quarter of 2003, respectively. Interest and other income (expense) of $0.4 million in the fourth quarter of 2003 represents interest rate driven investment income partially offset by amortization of issuance costs of the Zero Coupon Convertible Subordinated Notes due July 1, 2010. During the first quarter of 2004, we sold a portion of our UMC marketable securities holdings resulting in a gain of approximately $2.5 million. To the extent market conditions allow, we may make similar sales in future quarters. We are not currently paying federal or state income taxes and do not expect to pay or accrue such taxes in 2004.

Results of Operations

        The following table sets forth, for the periods indicated, the percentage of revenue represented by selected items reflected in our Consolidated Statement of Operations:

        Acquisitions.    On August 26, 2002, we completed the stock for stock acquisition of Cerdelinx Technologies, Inc. ("Cerdelinx") for 2.6 million shares valued at $8.30 per share. This transaction was accounted for as an asset purchase, and accordingly, the results of operations for Cerdelinx and estimated fair value of assets acquired and liabilities assumed are included in our consolidated financial statements beginning August 26, 2002. In estimating the fair value of the assets acquired, management considered various factors, including an appraisal. In-process research and development ("IPR&D") costs were appraised at $5.7 million and charged to operations on the acquisition date. Remaining intangible asset costs are being amortized to operations over a period averaging five years. See note 4 to our Consolidated Financial Statements.

        On January 18, 2002, we completed the acquisition of the field-programmable gate array ("FPGA") business ("Agere FPGA") of Agere Systems Inc. ("Agere") for $250 million in cash. This transaction was accounted for as a purchase, and accordingly, the results of operations for Agere FPGA and estimated fair value of assets acquired and liabilities assumed are included in our consolidated financial statements beginning January 18, 2002. In estimating the fair value of the assets acquired, management considered various factors, including an appraisal. IPR&D costs were appraised at $24.2 million and charged to operations on the acquisition date. Remaining intangible asset costs are being amortized to operations over 6.3 years. See note 5 to our Consolidated Financial Statements.

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        Revenue.    Revenue was $209.7 million in 2003, a decrease of nine percent from 2002. Revenue was $229.1 million in 2002, a decrease of 22% from 2001 revenue of $295.3 million. The composition of our revenue by product family for the years presented was as follows:

        Prior to the acquisition of Agere FPGA, we had no revenue from FPGA products.

        During 2003, our revenue was adversely affected by the business downturn experienced by the semiconductor and PLD markets that began in 2001, offset in part by a general business recovery experienced late in the year. Our revenue decrease in 2002 as compared to 2001 was a result of this 2001 downturn and the resultant decrease in demand for our products. Revenue declined across all geographies except Asia, and demand across most end markets remained weak.

        Our sales by geographic region were as follows (in thousands):

        Revenue from export sales as a percentage of total revenue was approximately 68% for 2003, 60% for 2002 and 54% for 2001. We expect export sales to continue to represent a significant portion of revenue.

        During 2003, total units sold and our overall average selling prices both decreased by approximately nine percent when compared to 2002. During 2002, total units sold decreased by 19% and our overall average selling price decreased by three percent when compared to 2001. Both units sold and average selling price were adversely impacted by the continued downturn in the semiconductor and PLD markets. Although selling prices of mature products generally decline over time, this decline is at times offset by higher selling prices of new products. Our ability to maintain or increase the level of our average selling price is dependent on the continued development, introduction and market acceptance of new products. See "Factors Affecting Future Results."

        Gross Margin.    Our gross margin percentage was 57% for 2003, 60% for 2002, and 62% for 2001. The decrease in gross margin percentage in 2003 is primarily attributable to provision for an allowance for price protection and sales returns for distributors in the September 2003 quarter. To a lesser extent, this decrease in gross margin also reflects the increased proportion of fixed manufacturing costs as a result of lower revenue levels. The decrease in gross margin percentage in 2002 as compared to 2001 was primarily due to the increased proportion of fixed manufacturing costs due to a decline in production volume. Reductions in our overall manufacturing costs and improvements in our product mix generally offset an increased proportion of fixed manufacturing costs in 2001. Product mix in 2001

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was favorably affected by a higher ratio of previously deferred income compared to income from direct customer sales. Reductions in manufacturing costs resulted primarily from on-going yield improvements, migration of products to more advanced technologies and smaller die sizes.

        Research and Development.    Research and development expense was $87.1 million for 2003 compared to $85.8 million for 2002 and $71.7 million in 2001. Research and development expenses consist primarily of labor, masks, prototype wafers, third-party design automation software, assembly tooling and qualification expenses. The increase in 2003 when compared to 2002 was primarily due to the continued development of new products. The increase in 2002 when compared to 2001 was primarily due to increased headcount and related spending due to our acquisition of Agere FPGA (see note 5 to our Consolidated Financial Statements). We believe that a continued commitment to research and development is essential in order to maintain product leadership and provide innovative new product offerings, and therefore we expect to continue to make significant future investments in research and development. As we continue to move to more advanced process technologies such as 130nm, 90nm and beyond, mask costs are becoming, and we believe will continue to become, significantly more expensive and will therefore increasingly represent a greater proportion of total research and development expenses.

        Selling, General and Administrative.    Selling, general and administrative expense was $50.8 million in 2003, $48.1 million in 2002, and $53.0 million in 2001. The increase in 2003 when compared to 2002 was primarily due to increased marketing expense related to new products and increased professional fees including those related to the restatement of the first, second and third quarter 2003 financial statements. The decrease in 2002 when compared to 2001 was primarily due to reduced revenue and associated reductions in variable costs and reductions in discretionary spending.

        In-Process Research and Development.    IPR&D consists of those products obtained through acquisition that are not yet proven to be technologically feasible but have been developed to a point where there is value associated with them in relation to potential future revenue. Because technological feasibility was not yet proven and no alternative future uses are believed to exist for the in-process technologies, the assigned value was expensed immediately upon the closing date of the acquisitions. IPR&D recorded in 2002 resulted from the completion of the Agere FPGA and Cerdelinx acquisitions described below:

Cerdelinx

        The fair value underlying the $5.7 million assigned to acquired IPR&D from the Cerdelinx acquisition (recognized in the third quarter of 2002) was determined by identifying research projects in areas for which technological feasibility had not been established and there were no alternative future uses. The acquired IPR&D consists of low-power CMOS transceivers and backplane interfaces with embedded high-speed SERDES I/O. These products were approximately 60% complete and were estimated to be completed in 2003 at an estimated cost of approximately $2 million. This project is now estimated to be complete in the first half of 2004. There has been no material change in the estimated cost of this project.

        The fair value was determined by an income approach where fair value is the present value of projected free cash flows that will be generated by the products incorporating the acquired technologies under development, assuming they are successfully completed. The estimated net free cash flows generated by the products over six year periods were discounted at rates ranging from 15% to 17% in relation to the stage of completion and the technical risks associated with achieving technological feasibility. The net cash flows for such projects were based on management's estimates of revenue, expenses and asset requirements.

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        All of these projects have completion risks related to silicon functionality, architecture performance, process technology availability, packaging technology, continued availability of key technical personnel and product reliability. To the extent that estimated completion dates are not met, the risk of competitive product introduction is greater and revenue opportunity may be permanently lost.

Agere FPGA

        The fair value underlying the $24.2 million assigned to acquired IPR&D in the Agere FPGA acquisition was determined by identifying research projects in areas for which technological feasibility had not been established and there was no alternative future use. Projects in the IPR&D category are the ORCA 4 FPGA family, the next generation FPGA family and the FPSC field-programmable system chips. The following is a brief description of these projects. The ORCA 4 FPGA family project, increasing speed and density and enhancing yields, was approximately 85% complete and estimated to be completed by 2003 at an estimated cost of $1.5 million. This project was completed during 2002 with no material change in cost. The next generation FPGA family project, increasing speed and density while reducing die size, was approximately 50% complete and estimated to be completed by 2004 at an estimated cost of $2 million. There has been no material change in the schedule or estimated cost of this project. The future development of FPSC field-programmable system chips (field-programmable system chips which combine embedded pre-defined logic circuits with an FPGA platform) was approximately 25% to 90% complete, and estimated to be completed by 2004 at an estimated cost of $2 million. There has been no material change in the schedule or estimated cost of this project. The IPR&D value of $24.2 million was determined by an income approach where fair value is the present value of projected free cash flows that will be generated by the products incorporating the acquired technologies under development, assuming they are successfully completed. The estimated net free cash flows generated by the products over 5-7 year periods were discounted at rates ranging from 23% to 25% in relation to the stage of completion and the technical risks associated with achieving technological feasibility. The net cash flows for such projects were based on management's estimates of revenue, expenses and asset requirements. Any delays or failures in the completion of these projects could impact our expected return on investment and future results. In addition, our financial condition would be adversely affected if the value of other intangible assets acquired became impaired.

        All of these projects have completion risks related to silicon functionality, architecture performance, process technology availability, packaging technology, continued availability of key technical personnel, product reliability and availability of software support. To the extent that estimated completion dates are not met, the risk of competitors' product introductions is greater and revenue opportunity may be permanently lost.

        Amortization of Intangible Assets.    Amortization of intangible assets is related to our 2002 acquisitions, discussed above, our 1999 Vantis acquisition and our 2001 acquisition of Integrated Intellectual Property, Inc. ("I2P"). Amortization expense was $77.1 million in 2003, $73.4 million in 2002, and $84.3 million in 2001. The increase in amortization for 2003 when compared with 2002 was due to a full year of amortization of intangible assets related to our 2002 acquisitions, and approximately $2.2 million incremental amortization of deferred stock compensation in association with the accelerated write-off of accrued deferred compensation recorded in conjunction with certain assumed in-the-money stock options as part of a stock option exchange program completed during the first quarter of 2003 (see note 12 to our Consolidated Financial Statements). The decrease in amortization for 2002 compared to 2001 was due to the cessation of amortizing goodwill in 2002 (see note 1 to our Consolidated Financial Statements) which more than offset the increased amortization of intangible assets related to our acquisitions of Agere FPGA and Cerdelinx.

        (Loss) Gain on Foundry Investments.    The loss on foundry investments recorded in the third quarter of 2001 represents impairment loss on our UMC common shares. In the September 2001

20

quarter, the carrying value of the UMC shares was reduced as we recorded a $152.8 million loss representing a decline in the market value of our UMC shares. In each quarter that the market value of the UMC investment is below carrying value, we evaluate whether the investment is other than temporarily impaired. We recorded the unrealized loss on our UMC investment in the September 30, 2001 Consolidated Statement of Operations. At that time, we believed the investment was other than temporarily impaired for the following reasons:

•

it was becoming increasingly likely that the stock price would not recover based on the increasing size of the unrealized loss, the extended time period during which the stock price had continued to decline without a trend reversal, and the dampening volatility, which indicated to us that the stock price was becoming more stable;



•

UMC's financial performance had weakened relative to earlier quarters;



•

the opinion of many industry observers and analysts regarding the semiconductor downturn had become significantly more negative;



•

the events of September 11, 2001 further exacerbated market conditions;



•

we had previously believed that UMC would initiate an ADR conversion program that would enable us to sell our shares at a premium on the New York Stock Exchange, but such a program was never initiated; and



•

although we still had the intent and ability to hold the shares for an indefinite period, we concluded this fact did not overcome the negative factors associated with the shares.

        Interest Income.    Interest income was $3.6 million in 2003, $5.4 million in 2002, and $17.7 million in 2001. The decrease in 2003 when compared to 2002 was due to lower interest rates on invested balances. The decrease in 2002 when compared to 2001 was due to lower invested balances as a result of our acquisition of Agere FPGA (see note 5 to our Consolidated Financial Statements) and lower interest rates on invested balances.

        Interest Expense.    Interest expense was approximately $7.1 million in 2003, $12.6 million in 2002 and $14.0 million in 2001. Substantially all interest expense resulted from the debt issued to partially fund our Vantis acquisition. The decrease in 2003 when compared to 2002 was due to the redemption of our remaining 4³/4% Convertible Subordinated Notes in July 2003. The decrease in 2002 when compared to 2001 is due to the extinguishment of approximately $51.9 million of our 4³/4% Convertible Subordinated Notes during the year (see note 11 to our Consolidated Financial Statements).

        Other Income.    Other income, net, was $0.4 million in 2003, $13.4 million in 2002 and $0.3 million in 2001. For 2003, Other income consists of gains recorded on the partial extinguishment of our convertible subordinated notes, substantially offset by the $4.7 million call premium associated with the redemption of our 4³/4% Convertible Subordinated Notes (see note 11 to our Consolidated Financial Statements). For 2002, the amount recorded consists primarily of a $9.3 million gain in conjunction with the extinguishment of a portion of our convertible subordinated notes (see note 11 to our Consolidated Financial Statements), and a $4.0 million gain in conjunction with the sale of a portion of our UMC shares (see note 7 to our Consolidated Financial Statements).

        (Benefit) Provision for Income Taxes.    The tax benefit in 2003 is primarily a result of releasing certain tax reserves ($3.4 million) as the related statute of limitations expired and a refund of Federal income taxes ($2.5 million). The provision for income taxes for 2002 of $81.9 million is primarily the result of a $118.6 million charge to income tax expense recorded in the fourth quarter of 2002, representing a full valuation allowance for our recorded deferred tax assets (see note 10 to our Consolidated Financial Statements). The tax benefit in 2001 is the result of the pretax loss reported in

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the period and the tax rate in 2001 is lower than the combined federal and statutory rates primarily because of tax exempt investment income and tax credits.

Critical Accounting Policies and Estimates

        Critical Accounting Policies are those "that are both most important to the portrayal of a company's financial condition and results and require management's most difficult, subjective and complex judgments, often as a result of the need to make estimates about the effect of matters that are inherently uncertain." A description of our critical accounting policies follows.

        Use of Estimates.    The preparation of financial statements in conformity with generally accepted accounting principles requires management to make estimates and assumptions that affect the reported amounts of assets, such as accounts receivable, inventory and deferred income taxes and liabilities, such as accrued liabilities, income taxes and deferred income, disclosure of contingent assets and liabilities at the date of the financial statements and the reported amounts of revenues and expenses during the fiscal periods presented. Actual results could differ from those estimates.

        Revenue recognition.    Revenue from direct customers is recognized upon shipment provided that persuasive evidence of a sales arrangement exists, the price is fixed and determinable, title has transferred, collection of resulting receivables is probable, there are no customer acceptance requirements and no remaining significant obligations. Certain of our sales are made to distributors under agreements providing price protection and right of return on unsold merchandise. Revenue and costs relating to such distributor sales are deferred until the product is sold by the distributor and related revenue and costs are then reflected in income.

        Our method of revenue recognition for deferred distributor sales is based on certain assumptions including our average collection experience compared to resale reported by the distributors. To the extent actual results differ from these assumptions, revenue will change accordingly.

        Deferred income.    In determining the balance in the deferred income account, we make estimates of salable and returnable inventory at certain distributors and we make estimates similar to those used to value inventory on hand to value inventory at these distributors. To the extent actual results differ from these estimates, the balances of reported deferred income, revenue and cost of products sold will change accordingly.

        Inventory.    We value inventory at the lower of cost or market on a quarterly basis. In addition, we write down unproven, excess and obsolete inventories to net realizable value. To value our inventory, we make a number of estimates and assumptions including future price declines and forecasted demand for our products. To the extent actual results differ from these estimates and assumptions, the balances of reported inventory and cost of products sold will change accordingly.

        Long-Lived Assets.    We account for our long-lived assets, primarily property and equipment and amortizable intangible assets, in accordance with Statement of Financial Accounting Standards ("SFAS") No. 144, "Accounting for the Disposal of Long-Lived Assets," which requires us to review the impairment of long-lived assets whenever events or changes in circumstances indicate that the carrying amount of an asset may not be recoverable. Impairment is measured by comparing the estimated undiscounted cash flows to the carrying amount. A loss is recorded if the carrying amount of the asset exceeds the estimated undiscounted cash flows. Intangible assets are generally being amortized over five years, and fifteen years for income tax purposes, on a straight-line basis.

        Accounting for income taxes.    To report income tax expense related to operating results, we record current and deferred income tax assets and liabilities in our balance sheet. In determining the value of our deferred tax assets, we make estimates of future taxable income. As of December 31, 2002 and 2003, we have recorded full valuation allowances for all of our deferred tax assets due to uncertainties

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regarding their realization. In determining the value of income tax liabilities, we make estimates of the results of future examinations of our income tax returns by taxing authorities. To the extent actual results differ from these estimates, our income tax provision will be affected accordingly.

New Accounting Pronouncements

        In January 2003, the Financial Accounting Standards Board ("FASB") issued Financial Standards Accounting Board Interpretation ("FIN") No. 46, "Consolidation of Variable Interest Entities," an interpretation of Accounting Research Bulletin No. 51, "Consolidated Financial Statements." FIN 46 establishes accounting guidance for consolidation of a variable interest entity. In a variable interest entity the equity investors do not have a controlling interest or their equity interest is insufficient to finance the entity's activities without receiving additional subordinated financial support from the other parties. We do not currently have any business relationship with a variable interest entity, so the adoption of FIN 46 had no impact on our consolidated financial position or results of operations.

        In April 2003, the FASB issued SFAS 149, "Amendment of Statement 133 on Derivative Instruments and Hedging Activities." This statement amends and clarifies financial accounting and reporting for derivative instruments, including certain derivative instruments embedded in other contracts, and for hedging activities under SFAS 133. SFAS 149 is effective for contracts entered into or modified after June 20, 2003. The adoption of SFAS 149 did not have a material effect on our results of operations, financial position or cash flows.

        In May 2003, the FASB issued SFAS 150, "Accounting for Certain Financial Instruments with Characteristics of both Liabilities and Equity." This pronouncement establishes standards for how an issuer classifies and measures in its statement of financial position certain financial instruments with characteristics of both liabilities and equity. It requires that an issuer classify a financial instrument that is within its scope as a liability (or an asset in certain circumstances) because that financial instrument embodies an obligation of the issuer. SFAS 150 is effective for financial instruments entered into or modified after May 31, 2003, and otherwise is effective for interim periods beginning after June 15, 2003. On November 7, 2003, FASB issued FASB Staff Position No. FAS 150-3 ("FSP 150-3"), "Effective Date, Disclosures, and Transition for Mandatorily Redeemable Financial Instruments of Certain Nonpublic Entities and Certain Mandatorily Redeemable Noncontrolling Interests under FASB Statement No. 150, Accounting for Certain Financial Instruments with Characteristics of Both Liabilities and Equity." FSP 150-3 deferred certain aspects of SFAS 150. The adoption of SFAS 150 and FSP 150-3 did not have a material impact on our results of operations, financial position or cash flows.

        On December 17, 2003, the Staff of the SEC issued Staff Accounting Bulletin No. 104 ("SAB 104"), "Revenue Recognition," which supersedes SAB 101, "Revenue Recognition in Financial Statements." SAB 104's primary purpose is to rescind accounting guidance contained in SAB 101 related to multiple element revenue arrangements, superseded as a result of the issuance of EITF 00-21, "Accounting for Revenue Arrangements with Multiple Deliverables." Additionally, SAB 104 rescinds the SEC's "Revenue Recognition in Financial Statements Frequently Asked Questions and Answers" (the "FAQ") issued with SAB 101 that had been codified in SEC Topic 13, "Revenue Recognition." Selected portions of the FAQ have been incorporated into SAB 104. While the wording of SAB 104 has changed to reflect the issuance of EITF 00-21, the revenue recognition principles of SAB 101 remain largely unchanged by the issuance of SAB 104. The adoption of SAB 104 did not materially affect our revenue recognition policies, nor our results of operations, financial position or cash flows.

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Liquidity and Capital Resources

        As of December 31, 2003, our principal source of liquidity was $277.6 million of cash and short-term investments, which was approximately flat with the balance of $276.9 million at December 31, 2002. Working capital increased to $363.6 million at December 31, 2003 from $348.8 million at December 31, 2002. This increase was primarily due to cash generated from operations. During 2003 we generated approximately $34.8 million of cash and cash equivalents from our operations compared with $46.0 million during 2002. This cash generation was primarily from refunds of federal income taxes previously paid due to net losses in 2001 and 2002.

        Inventories decreased by $9.6 million, or 17%, in 2003 as compared to the balance of the prior year primarily due to reduced starts and receipts of wafers in response to lower revenue levels. Prepaid expenses and other current assets decreased by approximately $18.9 million, or 54%, in 2003 as compared to the balance of the prior year. This decrease is due primarily to a decrease in refundable income taxes, offsetting an approximate $6.2 million increase in the amount of prepaid wafers expected to be used in the next twelve months (see note 7 to our Consolidated Financial Statements).

        Equity securities available for sale increased by $35.4 million, or 100%, in 2003 as compared to the balance in the prior year. These securities represent the portion of our investment in UMC that we expect to sell during 2004 (see notes 7 and 17 to our Consolidated Financial Statements). Foundry investments, advances and other assets decreased by approximately $17.6 million, or 17%, in 2003 as compared to the balance of the prior year. This was primarily due to the $35.4 million of our UMC investment reclassified to equity securities available for sale as described above and the $6.2 million reclassified to prepaid expenses and other current assets related to prepaid wafers described above, partially offset by a $24.6 million gain recorded in Accumulated other comprehensive (loss) income related to changes in the market value of our UMC shares. Property and equipment, less accumulated depreciation, decreased by $9.0 million, or 14%, in 2003 as compared to the balance in the prior year due to lower expenditures for capital equipment. Net intangible assets decreased by $71.3 million, or 46%, in 2003 as compared to the balance of the prior year which is attributable to amortization during 2003.

        On June 20, 2003, we issued $200 million in Zero Coupon Convertible Subordinated Notes due July 1, 2010. No interest will accrue or be payable related to these notes. Holders of these notes may convert the notes into shares of our common stock at any time before the close of business on the date of their maturity, unless the notes have been previously redeemed or repurchased, if (1) the price of our common stock issuable upon conversion of a note reaches a specified threshold, (2) the notes are called for redemption, (3) specified corporate transactions occur or (4) the trading price of the notes falls below certain thresholds. The conversion price is approximately $12.06 per share, subject to adjustment in certain circumstances. On or after July 1, 2008, we have the option to redeem all or a portion of the notes that have not been previously repurchased or converted at 100% of the principal amount of the notes. On July 1, 2008, holders have the option to require us to purchase all or a portion of their notes in cash at 100% of the principal amount of the notes. Holders also have the right, subject to certain conditions, to require us to repurchase the notes in the event of a "fundamental change" (as defined in the indenture governing the notes) at 100% of the principal amount of the notes. The notes are subordinated in right of payment to all of our senior indebtedness, and are structurally subordinated as to the revenues and assets of our subsidiaries to all debt and other liabilities of our subsidiaries. At December 31, 2003, we had no senior indebtedness and our subsidiaries had approximately $2.4 million of debt and other liabilities outstanding. Issuance costs relative to these convertible notes are included in "Foundry investments, advances and other assets" and aggregated approximately $5.4 million and are being amortized to expense over the lives of the notes. Accumulated amortization of these issuance costs was approximately $1.4 million as of December 31, 2003.

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        The estimated fair value of these convertible notes, based on quoted market prices, was approximately $192 million at December 31, 2003.

        In October 2003, our board of directors authorized management to repurchase up to $100 million of our Zero Coupon Convertible Subordinated Notes due July 1, 2010. During the third quarter of 2003, we extinguished approximately $16.0 million of these notes for approximately $14.2 million in cash and recognized a gain of approximately $1.4 million. In connection with this transaction, we also wrote off approximately $0.4 million of unamortized issuance costs.

        On July 21, 2003, we redeemed for cash all of our outstanding 4³/4% Convertible Subordinated Notes due in 2006, originally issued in October 1999, plus accrued interest. Total cash paid at redemption approximated $178.8 million, including par value of $172.3 million, accrued interest of approximately $1.8 million and a call premium of 2.71% of the outstanding notes, or approximately $4.7 million. This call premium, plus unamortized issuance costs of approximately $1.0 million as of the redemption date, was recorded as "Other expense" in the quarter ended September 30, 2003.

        During 2002, we extinguished approximately $51.9 million face value of our 4³/4% Convertible Subordinated Notes due in 2006 for approximately $42.8 million in cash, including accrued interest. We recognized a gain of approximately $9.3 million in connection with these transactions.

        Capital expenditures were approximately $9.7 million, $17.5 million and $13.8 million for 2003, 2002 and 2001, respectively. We expect to spend approximately $15 million to $20 million on capital expenditures for the fiscal year ending December 31, 2004.

        The following table summarizes our significant contractual cash obligations at December 31, 2003 (in thousands):

(1)

Certain of our facilities and equipment are leased under operating leases, which expire at various times through 2013. Rental expense under the operating leases was approximately $5.8 million, $6.0 million and $5.1 million for 2003, 2002 and 2001, respectively.

(2)

We depend entirely upon subcontractors to manufacture our silicon wafers. Other subcontractors provide substantially all our assembly and test services. Due to lengthy subcontractor lead times, we must order these materials and services well in advance, and we are obligated to pay for these materials and services once they are completed. We expect to receive and pay for these materials within the four to six months subsequent to December 31, 2003.

        Included in the above operating lease amounts are certain properties which are currently subleased. A portion of this sublease income is payable to the property owner. Future minimum

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sublease receipts, based on agreements in place at December 31, 2003, net of such payments are as follows (in thousands):

        As of December 31, 2003, we owned 91.7 million shares of UMC of which 23.3 million were restricted from sale for more than one year by the terms of our agreements with UMC. During 2002, we sold approximately 7.6 million of our UMC shares for approximately $9.9 million in cash, resulting in a gain of $4.0 million. During the first quarter of 2004, we sold 10.0 million of our UMC shares for approximately $9.2 million in cash, resulting in a gain of approximately $2.5 million. (see notes 7 and 17 to our Consolidated Financial Statements).

        In December 2000, our Board of Directors authorized management to repurchase up to five million shares of our common stock. As of December 31, 2003, we had repurchased 1,136,000 shares (596,000 in 2001) at an aggregate cost of approximately $20.0 million ($10.6 million in 2001). There were no repurchases of common stock in 2002 or 2003.

        In March 1997 and as subsequently amended in January 2002, we entered into an advance payment production agreement with Seiko Epson and Epson Electronics America, Inc. ("EEA") under which we agreed to advance up to approximately $69 million, payable upon completion of specific milestones, to Seiko Epson to finance construction of an eight-inch sub-micron semiconductor wafer manufacturing facility. Under the terms of the agreement, the advance is to be repaid with semiconductor wafers over a multi-year period. No interest income is recorded. The agreement calls for wafers to be supplied by Seiko Epson through EEA pursuant to purchase agreements with EEA. Payments of approximately $51.3 million have been made under this agreement. Cumulatively, approximately $15.6 million of these payments have been repaid to us in the form of semiconductor wafers. Approximately $9.9 million of the outstanding advances are expected to be repaid with semiconductor wafers during fiscal year 2004 and are thus reflected as part of Prepaid expenses and other current assets in our Consolidated Balance Sheet. We do not anticipate making additional payments under this agreement.

        In an effort to secure a long-term, stable advanced technology wafer supply, we plan to invest between $100 million and $200 million in Fujitsu's planned new 300mm wafer fab. Presently, we contemplate making this investment in stages before the end of 2005 and structuring the investment as an advance payment for production wafers and for access to future process technologies. The detailed terms of the investment are not yet finalized.

        We believe that our existing liquid resources and expected cash generated from operations combined with our ability to borrow additional funds will be adequate to meet our operating and capital requirements and obligations for the next 12 months. We may in the future seek new or additional sources of funding. In addition, in order to secure additional wafer supply, we may from time to time consider various financial arrangements including joint ventures, equity investments, advance purchase payments, loans, or similar arrangements with independent wafer manufacturers in exchange for committed wafer capacity. To the extent that we pursue any such additional financing arrangements, additional debt or equity financing may be required. There can be no assurance that such additional financing will be available when needed or, if available, will be on favorable terms. Any future equity financing will decrease existing stockholders' equity percentage ownership and may, depending on the price at which the equity is sold, result in dilution.

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Off-Balance Sheet Arrangements

        We do not have any financial partnerships with unconsolidated entities, such as entities often referred to as structured finance or special purpose entities, which are often established for the purpose of facilitating off-balance sheet arrangements or other contractually narrow or limited purposes. Accordingly, we are not exposed to any financing, liquidity, market or credit risk that could arise if we had such relationships.

Factors Affecting Future Results

A downturn in the communications equipment and computing end markets has caused a reduction in demand for our products and limited our ability to maintain or increase revenue levels and operating results.

        A significant portion of our revenue is derived from customers in the communications equipment and computing end markets. Due to a deterioration in overall economic conditions and a significant reduction in information technology capital spending, the communications and computing end markets have experienced a significant and prolonged downturn. While economic conditions in general, and the communications and computer end markets in particular, have recently shown signs of improvement, the improved conditions may not continue or lead to improved demand for our products. Whenever adverse economic or end market similar conditions exist, there is likely to be an adverse effect on our operating results.

We may be unsuccessful in defining, developing or selling new products required to maintain or expand our business.

        As a semiconductor company, we operate in a dynamic environment marked by rapid product obsolescence. Our future success depends on our ability to introduce new or improved silicon and software products that meet customer needs while achieving acceptable margins. If we fail to introduce these new products in a timely manner or these products fail to achieve market acceptance, our operating results would be harmed.

        The introduction of new silicon and software products in a dynamic market environment presents significant business challenges. Product development commitments and expenditures must be made well in advance of product sales. The market reception of new products depends on accurate projections of long-term customer demand, which by their nature are uncertain.

        Our future revenue growth is dependent on market acceptance of our new silicon and software product families and the continued market acceptance of our current products. The success of these products is dependent on a variety of specific technical factors including:

•

successful product definition;



•

timely and efficient completion of product design;



•

timely and efficient implementation of wafer manufacturing and assembly processes;



•

product performance;



•

product cost; and



•

the quality and reliability of the product.

        If, due to these or other factors, our new silicon and software products do not achieve market acceptance, our operating results would be harmed.

        In March 2004, we announced that Fujitsu Limited has agreed to manufacture our next generation FPGA products on its 130 nanometer and 90 nanometer CMOS process technologies, as well as on a 130 nanometer technology with embedded Flash memory that we are jointly developing with Fujitsu.

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The success of our future product launches is dependent on our ability to successfully partner with Fujitsu, which has not previously manufactured any of our products. If for any reason we are unsuccessful in our efforts to partner with Fujitsu in connection with these future product launches, our future revenue growth will be materially adversely affected.

The cyclical nature of the semiconductor industry may limit our ability to maintain or increase revenue levels and operating results during current or future industry downturns.

        The semiconductor industry is highly cyclical, to a greater extent than other less technology-driven industries. Our financial performance has periodically been negatively affected by downturns in the semiconductor industry. Factors that contribute to these industry downturns include:

•

the cyclical nature of the demand for the products of semiconductor customers;



•

general reductions in inventory levels by customers;



•

excess production capacity;



•

general decline in end-user demand; and



•

accelerated declines in average selling prices.

        Beginning in 2001, the semiconductor industry experienced a downturn of extreme severity and duration. While semiconductor industry conditions recently have improved, the improvement may not be significant or sustainable. Increased demand for semiconductor industry products may not proportionately increase demand for programmable logic market segment products in general, or our products in particular. Even if demand for our products increases, average sales prices for our products may not increase, and could decline. Whenever adverse semiconductor industry conditions or other similar conditions exist, there is likely to be an adverse effect on our operating results.

Our products may not be competitive if we are unsuccessful in migrating our manufacturing processes to more advanced technologies or alternative fabrication facilities.

        To develop new products and maintain the competitiveness of existing products, we need to migrate to more advanced wafer manufacturing processes that use larger wafer sizes and smaller device geometries. We also may need to use additional foundries. Because we depend upon foundries to provide their facilities and support for our process technology development, we may experience delays in the availability of advanced wafer manufacturing process technologies at existing or new wafer fabrication facilities. As a result, volume production of our advanced process technologies at the fabs of Seiko Epson, UMC, Chartered Semiconductor, Fujitsu or future foundries may not be achieved. This could harm our operating results.

We face risks related to our recent accounting restatement.

        On January 22, 2004, we announced that we had discovered possible accounting inaccuracies in previously reported quarterly financial statements. An internal investigation was conducted by the Audit Committee of our Board of Directors to determine the scope and magnitude of these inaccuracies. On March 24, 2004, we announced that the Audit Committee had completed its internal accounting investigation and, as a result, we were required to restate our financial statements for the first, second and third quarters of 2003 to correct inappropriate accounting entries and a failure to record a change in accounting estimate related to deferred income.

        The restatement of these financial statements may lead to litigation claims and/or regulatory proceedings against us. The defense of any such claims or proceedings may cause the diversion of management's attention and resources, and we may be required to pay damages if any such claims or proceedings are not resolved in our favor. Any litigation or regulatory proceeding, even if resolved in our favor, could cause us to incur significant legal and other expenses. Moreover, we may be the

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subject of negative publicity focusing on the financial statement inaccuracies and resulting restatement. The occurrence of any of the foregoing could harm our business and reputation and cause the price of our common stock to decline.

If we are unable to effectively and efficiently implement our plan to remediate a material weakness that has been identified in our internal controls and procedures, there could be a material adverse effect on our operations or financial results.

        We received notice from our independent auditor that, in connection with the 2003 year-end audit, the auditor has identified a material weakness in our internal controls and procedures relating to separation of duties and establishment of standards for review of journal entries and related file documentation. We have implemented and are continuing to implement various initiatives intended to materially improve our internal controls and procedures to address this weakness. These initiatives address our control environment, organization and staffing, policies, procedures and documentation, and information systems. The implementation of these initiatives is one of our highest priorities. Our Board of Directors, in coordination with our Audit Committee, will continually assess the progress and sufficiency of these initiatives and make adjustments as necessary. However, no assurance can be given that we will be able to successfully implement our revised internal controls and procedures or that our revised controls and procedures will be effective in remedying all of the identified deficiencies in our internal controls and procedures. In addition, we may be required to hire additional employees, and may experience higher than anticipated capital expenditures and operating expenses, during the implementation of these changes and thereafter. If we are unable to implement these changes effectively or efficiently, there could be a material adverse effect on our operations or financial results. Moreover, we could be subject to additional regulatory oversight and our business and reputation could be harmed.

        In addition, we may in the future experience accounting estimate changes related to our deferred income account, inventory account, income tax liability, accounts receivable collectibility, or realization of goodwill and intangible assets, any of which could adversely affect our financial results.

Our future quarterly operating results may fluctuate and therefore may fail to meet expectations.

        Our quarterly operating results have fluctuated and may continue to fluctuate. Consequently, our operating results may fail to meet the expectations of analysts and investors. As a result of industry conditions and the following specific factors, our quarterly operating results are more likely to fluctuate and are more difficult to predict than a typical non-technology company of our size and maturity:

•

general economic conditions in the countries where we sell our products;



•

conditions within the end markets into which we sell our products;



•

the cyclical nature of demand for our customers' products;



•

excessive inventory accumulation by our end customers;



•

the timing of our and our competitors' new product introductions;



•

product obsolescence;



•

the scheduling, rescheduling and cancellation of large orders by our customers;



•

our ability to develop new process technologies and achieve volume production at the fabs of Seiko Epson, UMC, Chartered Semiconductor, Fujitsu or at other foundries;



•

changes in manufacturing yields;



•

adverse movements in exchange rates, interest rates or tax rates; and

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•

the availability of adequate supply commitments from our wafer foundries and assembly and test subcontractors.

        As a result of these factors, our past financial results are not necessarily a good predictor of our future results.

Our stock price may continue to experience large fluctuations.

        In recent years, the price of our common stock has fluctuated greatly. These price fluctuations have been rapid and severe and have left investors little time to react. The price of our common stock may continue to fluctuate greatly in the future due to a variety of company specific factors, including:

•

quarter-to-quarter variations in our operating results;



•

shortfalls in revenue or earnings from levels expected by securities analysts; and



•

announcements of technological innovations or new products by other companies.

        Presently, our stock price is trading near our consolidated book value. A sustained decline in our stock price may result in a write-off of goodwill (see Note 1 of our Consolidated Financial Statements).

Our wafer supply may be interrupted or reduced, which may result in a shortage of finished products available for sale.

        We do not manufacture finished silicon wafers. Currently, substantially all of our silicon wafers are manufactured by Seiko Epson in Japan, UMC in Taiwan, and Chartered Semiconductor in Singapore. In March 2004 we announced that we will also be sourcing wafers on advanced process technologies from Fujitsu in Japan. If any of our current or future foundry partners significantly interrupts or reduces our wafer supply, our operating results could be harmed.

        In the past, we have experienced delays in obtaining wafers and in securing supply commitments from our foundries. At present, we anticipate that our supply commitments are adequate. However, these existing supply commitments may not be sufficient for us to satisfy customer demand in future periods. Additionally, notwithstanding our supply commitments we may still have difficulty in obtaining wafer deliveries consistent with the supply commitments. We negotiate wafer prices and supply commitments from our suppliers on at least an annual basis. If any of our foundry partners were to reduce its supply commitment or increase its wafer prices, and we cannot find alternative sources of wafer supply, our operating results could be harmed.

        Many other factors that could disrupt our wafer supply are beyond our control. Since worldwide manufacturing capacity for silicon wafers is limited and inelastic, we could be harmed by significant industry-wide increases in overall wafer demand or interruptions in wafer supply. Additionally, a future disruption of any of our foundry partners' foundry operations as a result of a fire, earthquake or other natural disaster could disrupt our wafer supply and could harm our operating results.

If our foundry partners experience quality or yield problems, we may face a shortage of finished products available for sale.

        We depend on our foundries to deliver reliable silicon wafers with acceptable yields in a timely manner. As is common in our industry, we have experienced wafer yield problems and delivery delays. If our foundries are unable for a prolonged period to produce silicon wafers that meet our specifications, with acceptable yields, our operating results could be harmed.

        The majority of our revenue is derived from products based on a specialized silicon wafer manufacturing process technology called E²CMOS®. The reliable manufacture of high performance E²CMOS semiconductor wafers is a complicated and technically demanding process requiring:

•

a high degree of technical skill;

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•

state-of-the-art equipment;



•

the absence of defects in the masks used to print circuits on a wafer;



•

the elimination of minute impurities and errors in each step of the fabrication process; and



•

effective cooperation between us and the wafer supplier.

        As a result, our foundries may experience difficulties in achieving acceptable quality and yield levels when manufacturing our silicon wafers.

If our assembly and test contractors experience quality or yield problems, we may face a shortage of finished products available for sale.

        We rely on contractors to assemble and test our devices with acceptable quality and yield levels. As is common in our industry, we have experienced quality and yield problems in the past. If we experience prolonged quality or yield problems in the future, our operating results could be harmed.

        The majority of our revenue is derived from semiconductor devices assembled in advanced packages. The assembly of advanced packages is a complex process requiring:

•

a high degree of technical skill;



•

state-of-the-art equipment;



•

the absence of defects in lead frames used to attach semiconductor devices to the package;



•

the elimination of raw material impurities and errors in each step of the process; and



•

effective cooperation between us and the assembly contractor.

        As a result, our contractors may experience difficulties in achieving acceptable quality and yield levels when assembling and testing our semiconductor devices.

Deterioration of conditions in Asia may disrupt our existing supply arrangements and result in a shortage of finished products available for sale.

        All of our major silicon wafer suppliers operate fabs located in Asia. Our finished silicon wafers are assembled and tested by independent contractors located in China, Malaysia, the Philippines, South Korea and Taiwan. A prolonged interruption in our supply from any of these contractors could harm our operating results.

        Economic, financial, social and political conditions in Asia have historically been volatile. Financial difficulties, governmental actions or restrictions, prolonged work stoppages or any other difficulties experienced by our suppliers may disrupt our supply and could harm our operating results.

        Our wafer purchases from Seiko Epson are denominated in Japanese yen. The value of the dollar with respect to the yen fluctuates. Substantial deterioration of dollar-yen exchange rates could harm our operating results.

Export sales account for a substantial portion of our revenues and may decline in the future due to economic and governmental uncertainties.

        Our export sales are affected by unique risks frequently associated with foreign economies including:

•

changes in local economic conditions;



•

exchange rate volatility;



•

governmental controls and trade restrictions;



•

export license requirements and restrictions on the export of technology;

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•

political instability or terrorism;



•

changes in tax rates, tariffs or freight rates;



•

interruptions in air transportation; and



•

difficulties in staffing and managing foreign sales offices.

        For example, our export sales have historically been affected by regional economic crises. Significant changes in the economic climate in the foreign countries where we derive our export sales could harm our operating results.

We may not be able to successfully compete in the highly competitive semiconductor industry.

        The semiconductor industry is intensely competitive and many of our direct and indirect competitors have substantially greater financial, technological, manufacturing, marketing and sales resources. If we are unable to compete successfully in this environment, our future results will be adversely affected.

        The current level of competition in the programmable logic market is high and may increase in the future. We currently compete directly with companies that have licensed our technology or have developed similar products. We also compete indirectly with numerous semiconductor companies that offer products and solutions based on alternative technologies. These direct and indirect competitors are established multinational semiconductor companies as well as emerging companies. We also may experience significant competition from foreign companies in the future.

We may fail to retain or attract the specialized technical and management personnel required to successfully operate our business.

        To a greater degree than most non-technology companies or larger technology companies, our future success depends on our ability to attract and retain highly qualified technical and management personnel. As a mid-sized company, we are particularly dependent on a relatively small group of key employees. Competition for skilled technical and management employees is intense within our industry. As a result, we may not be able to retain our existing key technical and management personnel. In addition, we may not be able to attract additional qualified employees in the future. If we are unable to retain existing key employees or are unable to hire new qualified employees, our operating results could be adversely affected.

If we are unable to adequately protect our intellectual property rights, our financial results and competitive position may suffer.

        Our success depends in part on our proprietary technology. However, we may fail to adequately protect this technology. As a result, we may lose our competitive position or face significant expense to protect or enforce our intellectual property rights.

        We intend to continue to protect our proprietary technology through patents, copyrights and trade secrets. Despite this intention, we may not be successful in achieving adequate protection. Claims allowed on any of our patents may not be sufficiently broad to protect our technology. Patents issued to us also may be challenged, invalidated or circumvented. Finally, our competitors may develop similar technology independently.

        Companies in the semiconductor industry vigorously pursue their intellectual property rights. If we become involved in protracted intellectual property disputes or litigation we may utilize substantial financial and management resources, which could have an adverse effect on our operating results.

        Our industry is characterized by frequent claims regarding patents and other intellectual property rights of others. We have been, and from time-to-time expect to be, notified of claims that we are infringing the intellectual property rights of others. If any third party makes a valid claim against us, we

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could face significant liability and could be required to make material changes to our products and processes. In response to any claims of infringement, we may seek licenses under patents that we are alleged to be infringing. However, we may not be able to obtain a license on favorable terms or without our operating results being adversely affected.

Our marketable securities, which we hold for strategic reasons, are subject to equity price risk and their value may fluctuate.

        Currently we hold substantial equity in UMC, which we acquired as part of a strategic investment to obtain certain manufacturing rights. The market price and valuation of these equity shares has fluctuated widely due to market and other conditions over which we have little control. During the year ended December 31, 2001, we recorded a $152.8 million pre-tax impairment loss related to this investment. In the future, UMC shares may continue to experience significant price volatility. In the second quarter of 2002 and the first quarter of 2004, we sold a portion of our UMC shares, but have otherwise not attempted to reduce or eliminate this equity price risk through hedging or similar techniques and hence substantial, sustained changes in the market price of UMC shares could impact our financial results. To the extent that the market value of our UMC shares experiences a significant decline for an extended period of time, our net income could be reduced.

Item 7(a) Quantitative and Qualitative Disclosures About Market Risk

        As of December 31, 2003 and December 31, 2002 our investment portfolio consisted of fixed income securities of $275.0 million and $274.4 million, respectively. As with all fixed income instruments, these securities are subject to interest rate risk and will decline in value if market interest rates increase. If market rates were to increase immediately and uniformly by 10% from levels as of December 31, 2003 and December 31, 2002, the decline in the fair value of our portfolio would not be material. Further, we have the ability to hold our fixed income investments until maturity and, therefore, we would not expect to recognize such an adverse impact in our income or cash flows.

        We have international subsidiary and branch operations. Additionally, some of our silicon wafer purchases are denominated in Japanese yen. We therefore are subject to foreign currency rate exposure. To mitigate rate exposure with respect to our yen-denominated wafer purchases, we maintain a yen-denominated bank account and bill our Japanese customers in yen. If the foreign currency rates were to fluctuate by 10% from rates at December 31, 2003 and December 31, 2002, the effect on our consolidated financial statements would not be material. However, there can be no assurance that there will not be a material impact in the future.

        We are exposed to equity price risk due to our equity investment in UMC (see note 7 to our Consolidated Financial Statements). Neither a 10% increase nor a further 10% decrease in equity price related to this investment would have a material effect on our consolidated financial statements. We have not attempted to reduce or eliminate this equity price risk through hedging or similar techniques. As a result, sustained changes in the market price of UMC shares could impact our financial results. To the extent that the market value of our UMC shares experiences further deterioration for an extended period of time, our net income could be reduced.

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Item 8. Financial Statements and Supplementary Data.

Index to Consolidated Financial Statements and Consolidated Financial Statement Schedules

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LATTICE SEMICONDUCTOR CORPORATION
CONSOLIDATED BALANCE SHEET
(In thousands, except share and par value amounts)

The accompanying notes are an integral part of this statement

35

LATTICE SEMICONDUCTOR CORPORATION
CONSOLIDATED STATEMENT OF OPERATIONS
(In thousands, except per share amounts)

(1)

Includes $5,745, $2,962 and $397 of amortization of deferred stock compensation expense for the years ended December 31, 2003, December 31, 2002 and December 31, 2001, respectively attributable to research and development activities.

The accompanying notes are an integral part of this statement

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LATTICE SEMICONDUCTOR CORPORATION
CONSOLIDATED STATEMENT OF CHANGES IN STOCKHOLDERS' EQUITY
(In thousands, except par value)