Back to GetFilings.com

UNITED STATES
SECURITIES AND EXCHANGE COMMISSION
Washington, D.C 20549

FORM 10-K

LATTICE SEMICONDUCTOR CORPORATION
(Exact name of Registrant as specified in its Charter)

Registrant's telephone number, including area code: (503) 268-8000

Securities registered pursuant to Section 12(b) of the Act: None
Securities registered pursuant to Section 12(g) of the Act:

    Indicate by check mark whether the Registrant (1) has filed all reports required to be filed by Section 13 or 15(d) of the Securities Exchange Act of 1934 during the preceding 12 months (or for such shorter period that the Registrant was required to file such reports), and (2) has been subject to such filing requirements for the past 90 days. Yes /x/  No / /

    Indicate by check mark if disclosure of delinquent filers pursuant to Item 405 of Regulation S-K is not contained herein, and will not be contained, to the best of the Registrant's knowledge, in definitive proxy or information statements incorporated by reference in Part III of this Form 10-K or any amendment to this Form 10-K. Yes / /  No /x/

    As of March 15, 2001, the aggregate market value of the shares of voting stock of the Registrant held by non-affiliates was approximately $1.094 billion. Shares of Common Stock held by each officer and director and by each person who owns 5% or more of the outstanding Common Stock have been excluded in that such persons may be deemed affiliates. This determination of affiliate status is not necessarily a conclusive determination for other purposes.

    As of March 15, 2001, 108,486,807 shares of the Registrant's common stock were outstanding.

DOCUMENTS INCORPORATED BY REFERENCE

    1.  Portions of the Annual Report to Stockholders for the fiscal year ended December 30, 2000 are incorporated by reference in Part II hereof.

    2.  Portions of the definitive proxy statement of the Registrant to be filed pursuant to Regulation 14A for the 2001 Annual Meeting of Stockholders to be held on May 1, 2001 are incorporated by reference in Part III hereof.

LATTICE SEMICONDUCTOR CORPORATION
FORM 10-K
ANNUAL REPORT
TABLE OF CONTENTS

1

Item 1. Business

BUSINESS

    Lattice Semiconductor Corporation designs, develops and markets high performance programmable logic devices, or PLDs, and related software. Programmable logic devices are widely-used semiconductor components that can be configured by the end customer as specific logic circuits, and enable the end customer to shorten design cycle times and reduce development costs. Our end customers are primarily original equipment manufacturers in the markets of data communications and telecommunications, as well as computing, industrial and military systems.

    In 1999, we acquired Vantis Corporation, the programmable logic device subsidiary of Advanced Micro Devices ("AMD"). This acquisition has increased our share of the PLD market, accelerated development of new products and technologies and expanded our penetration into new and existing customers.

Change in Fiscal Reporting Period

    In the fourth quarter of calendar 1999, we changed our reporting period to a 52 or 53 week year ending on the Saturday closest to December 31 from a 52 or 53 week fiscal year ending on the Saturday closest to March 31. For ease of presentation, December 31 or March 31 has been utilized as the fiscal period end date for all financial statement captions. Additionally, for purposes of our consolidated financial statements and this Annual Report, our fiscal year ended December 30, 2000 is referrred to as "the year ended December 31, 2000," or "2000." The nine-month fiscal period ended January 1, 2000 is referred to as "the nine months ended December 31, 1999" or "fiscal period 1999." Our fiscal year ended on April 3, 1999 is referred to as "the fiscal year ended March 31, 1999" or "fiscal year 1999." The fiscal year ended April 3, 1999 was a 53-week fiscal year.

PLD Market Background

    Three principal types of digital integrated circuits are used in most electronic systems: microprocessors, memory and logic. Microprocessors are used for control and computing tasks, memory is used to store programming instructions and data, and logic is employed to manage the interchange and manipulation of digital signals within a system. Logic contains interconnected groupings of simple logical "and" and logical "or" functions, commonly described as "gates." Typically, complex combinations of individual gates are required to implement the specialized logic functions required for systems applications. While system designers use a relatively small number of standard architectures to meet their microprocessor and memory needs, they require a wide variety of logic circuits in order to achieve end product differentiation.

    Logic circuits are found in a wide range of today's digital electronic equipment including communication, computing, industrial and military systems. According to World Semiconductor Trade Statistics, a semiconductor industry association, logic accounted for approximately 26% of the estimated $174 billion worldwide digital integrated circuit market in 2000. The logic market encompasses, among other segments, standard logic, custom-designed application specific integrated circuits, or ASICs, which include conventional gate-arrays, standard cells and full custom logic circuits, and PLDs.

    Manufacturers of electronic equipment are challenged to bring differentiated products to market quickly. These competitive pressures often preclude the use of custom-designed ASICs, which generally entail significant design risks, non-recurring costs and time delays. Standard logic products, an alternative to custom-designed ASICs, limit a manufacturer's flexibility to adequately customize an end system. PLDs address this inherent dilemma. PLDs are standard products, purchased by systems manufacturers in a "blank" state, that can be custom configured into a virtually unlimited number of specific logic functions by programming the device with electrical signals. PLDs give system designers

2

the ability to quickly create custom logic functions to provide product differentiation without sacrificing rapid time to market. Certain PLD products, including our own, are reprogrammable, meaning that the logic configuration can be modified, if needed, after the initial programming. ISP™ PLDs, pioneered by us, extend the flexibility of standard reprogrammable PLDs by allowing the system designer to configure and reconfigure the logic functions of the PLD with standard 5-volt or 3.3-volt power supplies without removing the PLD from the system board.

    According to Dataquest, the PLD market in 2000 was approximately $4.1 billion. The PLD market has two primary segments: low-density PLDs, with fewer than 1,000 logic gates, and high-density PLDs, with more than 1,000 logic gates. High-density PLD devices include devices based on both the CPLD and field programmable gate array, or FPGA, architectures. In 2000, CPLD represented a $1.2 billion market and FPGA a $2.7 billion market.

    Products based on these alternative high density PLD architectures are generally optimal for different types of logic functions, although many logic functions can be implemented using either architecture. CPLDs are characterized by a regular building block structure of wide-input logic cells, called macrocells, and use of a centralized logic interconnect scheme. FPGAs are characterized by a narrow-input logic cell and use a distributed interconnect scheme. Although CPLDs and FPGAs are better suited for use in different types of logic applications, we believe that a substantial portion of high-density PLD customers utilize both CPLD and FPGA architectures within a single system design, partitioning logic functions across multiple devices to optimize overall system performance and cost.

    A growing percentage of the PLD market is made up of devices which operate using 3.3-volt and 2.5-volt power supplies. Lower voltage PLDs benefit end users by consuming less power and providing compatibility with other advanced electronic components. We believe that our innovative low-voltage CPLD products provide us a competitive advantage in the emerging market for low voltage PLDs.

Technology

    We believe that our proprietary E²CMOS® technology is the preferred process technology for PLD products due to its inherent performance, reprogrammability and testability benefits. E²CMOS technology, through its fundamental ability to be programmed and erased electronically, serves as the foundation for our ISP products.

    We pioneered the development of in-system programmability™ which has become an industry standard feature in the PLD market. Our ISP devices use either 5-volt or 3.3-volt programming signals and, as a result, can be configured and reconfigured by a system designer without being removed from the printed circuit board. Standard E²CMOS PLDs require a 12-volt programming signal and therefore must be removed from the printed circuit board and programmed using specialized hardware. Our ISP devices offer enhanced flexibility compared to standard PLDs and provide significant benefits to our customers. Our ISP devices can allow customers to reduce design cycle times, accelerate time to market, reduce prototyping costs, reduce manufacturing costs and lower inventory requirements. Our ISP devices can also provide customers the opportunity to perform simplified and cost-effective field reconfiguration through a data file transferred by computer disk or serial data signal.

Products

    We strive to offer innovative and differentiated programmable solutions based on our proprietary technology.

High Density Products

    Since 1992, we have focused on developing an industry leading portfolio of high density CPLD products and increasing the percentage of our overall revenue derived from this attractive market. At

3

present we offer the broadest range of CPLD products in the marketplace. During 2000, approximately 76% of our revenues were derived from high density products, as compared to 66% in calendar 1999 and essentially zero in 1992. In the future, we plan to continue to introduce new families of innovative, high performance and higher density programmable products, as well as improve the performance and reduce the manufacturing cost of our existing product families based on market needs.

    The key features of our CPLD product families are described in the table below:

    Our newest product families, the ispMACH 4A, ispLSI 2000VE, ispLSI 5000VE and ispLSI 8000V, use innovative architectures and are targeted towards the emerging low voltage portion of the CPLD market.

    ispGDX®/V.  We also offer two additional high density product families, ispGDX and ispGDXV, that target a unique aspect of the programmable logic market. These families extend in-system programmability to the circuit board level using an innovative digital cross-point switch architecture. Offered with propagation delays as low as 3.5 nanoseconds, up to 240 input/output pins and complete pin-to-pin signal routing, both the 5-volt ispGDX and the 3.3-volt ispGDXV are targeted towards digital signal interconnect and interface applications.

Mixed Signal Products

    During 1999, we added mixed signal products to our portfolio as we believe these devices provide an opportunity to extend our proprietary technology to an untapped potential market.

    ispPAC® Products.  This three device family extends in-system programmability to the analog market. The innovative architecture of the ispPAC allows designers to quickly and easily program resistor and capacitor values, gain and signal polarity and circuit interconnect to implement a wide variety of analog circuits. The initial ispPAC products are targeted towards filtering and signal conditioning applications and can replace numerous discrete analog components. ispPAC designs are implemented and programmed via a personal computer using our software development tool, PAC-Designer®.

Software Development Tools

    All Lattice ISP products are supported by ispDesignEXPERT™, our fourth generation software development tool suite. Supporting both the PC and UNIX platforms, ispDesignEXPERT allows a customer to enter, verify and synthesize a design, perform logic simulation and timing analysis, assign input/output pins and critical speed paths, debug and floorplan a design, execute automatic place and route tasks and download a program to an ISP device. Seamlessly integrated with third-party electronic design automation, or EDA, environments, ispDesignEXPERT leverages customers' prior investments in products offered by Aldec, Cadence, Innoveda, Mentor Graphics, OrCAD, Synopsys, Synplicity and Veribest. In the future, we plan to continue to enhance and expand the capability of our software development tool suite.

4

    We also provide a variety of software algorithms that support in-system programming of our ISP devices via multiple formats and mechanisms. These software products include Turbo isp DOWNLOAD®, ispATE®, ispSVF™ and ispVM™.

Low Density PLD Products

    We offer the industry's broadest line of low-density CMOS PLDs based on our 22 families of GAL® and PALCE™ products offered in over 200 speed, power, package and temperature range combinations. PALCE products were originally introduced by Vantis and are generally compatible with GAL products. GAL and PALCE devices range in complexity from approximately 200 to 1,000 logic gates and are typically assembled in 20-, 24- and 28-pin standard dual in-line packages and in 20- and 28-pin standard plastic leaded chip carrier packages. We offer standard 610, 16V8, 20V8 and 22V10 architectures in a variety of speed grades, with propagation delays as low as 3.5 nanoseconds, the highest performance in the industry. In addition, we offer several proprietary extension architectures, the isp22V10, 6001/2, 16VP8, 16V8Z, 18V10, 20VP8, 20V8Z, 22V10Z, 24V10, 29M16, 20RA10, 20XV10 and 26V12, each of which is optimized for specific applications. We also offer a full range of 3.3-volt standard architectures, the isp22LV10, 16LV8, 20LV8, 22LV10 and 26CLV12, in a variety of speed grades, with propagation delays as low as 3.5 nanoseconds, the highest performance in the industry.

Product Development

    We place substantial emphasis on new product development and believe that continued investment in this area is required to maintain our competitive position. Our product development activities emphasize new proprietary ISP products, enhancement of existing products and process technologies and improvement of software development tools. Product development activities occur in Hillsboro, Oregon; San Jose, California; Austin, Texas; Colorado Springs, Colorado; Corsham, England; and Shanghai, China.

    Research and development expenses were $33.2 million in fiscal year 1999, $45.9 million for fiscal period 1999 and $77.1 million in 2000. We expect to continue to make significant future investments in research and development.

Operations

    We do not manufacture our own silicon wafers. We maintain strategic relationships with large semiconductor manufacturers to source our finished silicon wafers. This strategy allows us to focus our internal resources on product, process and market development, and eliminates the fixed cost of owning and operating manufacturing facilities. We are also able to take advantage of the ongoing advanced process technology dedicated development efforts of semiconductor manufacturers. In addition, all of our assembly operations are performed by outside suppliers. We perform certain test operations and reliability and quality assurance processes internally. We have achieved an ISO 9001 quality certification, an indication of our high internal operational standards.

Wafer Fabrication

    We source a portion of our silicon wafer requirements from Seiko Epson in Japan pursuant to an agreement with Epson Electronics America, an affiliated U.S. distributor of Seiko Epson. We negotiate wafer volumes, prices and terms with Seiko Epson and Epson Electronics America on a periodic basis. We also source silicon wafers from the UMC Group in Taiwan pursuant to a series of agreements entered into in 1995. Wafer prices and other purchase terms related to this commitment are subject to periodic adjustment. We also source silicon wafers for our mature MACH and PALCE products from AMD pursuant to an agreement first entered into in 1996 and subsequently amended and restated at the time of our acquisition of Vantis.

5

Assembly

    After wafer fabrication and initial testing, we ship wafers to independent subcontractors for assembly. During assembly, wafers are separated into individual die and encapsulated in plastic or ceramic packages. Presently, we have qualified long-term assembly partners in Hong Kong, Malaysia, the Philippines, Singapore, South Korea, Taiwan and Thailand.

Testing

    We electrically test the die on each wafer prior to shipment for assembly. Following assembly, prior to customer shipment, each product undergoes final testing and quality assurance procedures. Final testing on certain products is performed by independent contractors in Malaysia, the Philippines, South Korea, Taiwan, Thailand and the United States.

Marketing, Sales and Customers

    We sell our products directly to end customers through a network of independent manufacturers' representatives and indirectly through a network of independent distributors. We also employ a direct sales management and field applications engineering organization to support our end customers and indirect sales resources. Our end customers are primarily original equipment manufacturers in the fields of communication, computing, industrial and military systems.

    As of December 2000, we used 24 manufacturers' representatives and three distributors in North America. Arrow Electronics and Avnet provide full distribution coverage. We have also established export sales channels in over 30 foreign countries through a network of over 30 sales representatives and distributors. Approximately one-half of our North American sales and the majority of our export sales are made through distributors.

    We protect each of our North American distributors and some of our foreign distributors against reductions in published prices, and expect to continue this policy in the foreseeable future. We also allow returns from these distributors of unsold products under certain conditions. For these reasons, we do not recognize revenue until products are resold by these distributors to an end customer.

    We provide technical and marketing support to our end customers with engineering staff based at our headquarters, design centers and selected field sales offices. We maintain numerous domestic and international field sales offices in major metropolitan areas.

    Export sales as a percentage of our total revenue were 50% in fiscal year 1999, 53% in fiscal period 1999 and 57% in 2000. Both export and domestic sales are denominated in U.S. dollars, with the exception of sales to Japan, which are dominated in yen. If our export sales decline significantly there would be a material adverse impact on our business.

    Our products are sold to a large and diverse group of customers. No individual end customer accounted for more than 10% of total revenue in fiscal year 1999, fiscal period 1999 or 2000. No export sales to any given country accounted for more than 10% of total revenue in fiscal year 1999, fiscal period 1999 or 2000.

Backlog

    Our backlog of scheduled and released orders as of December 31, 2000 was approximately $85.9 million as compared to approximately $83.4 million as of December 31, 1999. This backlog consists of direct OEM and distributor orders scheduled for delivery within the next 90 days. Distributor orders accounted for the majority of the backlog in both periods. Direct OEM customer orders may be changed, rescheduled or cancelled under certain circumstances without penalty prior to shipment. Additionally, distributor orders generally may be changed, rescheduled or cancelled without

6

penalty prior to shipment. Furthermore, distributor shipments are subject to rights of return and price adjustment. Revenue associated with distributor shipments is not recognized until the product is resold to an end customer. Typically, the majority of our revenue results from orders placed and filled within the same period. Such orders are referred to as "turns orders." By definition, turns orders are not captured in a backlog measurement made at the beginning of a period. We do not anticipate a significant change in this business pattern. For all these reasons, backlog as of any particular date should not be used as a predictor of revenue for any future period.

Competition

    The semiconductor industry is intensely competitive and characterized by rapid rates of technological change, product obsolescence and price erosion. Our current and potential competitors include a broad range of semiconductor companies from large, established companies to emerging companies, many of which have greater financial, technical, manufacturing, marketing and sales resources.

    The principal competitive factors in the PLD market include product features, price, customer support, and sales, marketing and distribution strength. The availability of competitive software development tools is also critical. In addition to product features such as density, speed, power consumption, reprogrammability, design flexibility and reliability, competition in the PLD market occurs on the basis of price and market acceptance of specific products and technology. We believe that we compete favorably with respect to each of these factors. We intend to continue to address these competitive factors by working to continually introduce product enhancements and new products, by seeking to establish our products as industry standards in their respective markets, and by working to reduce the manufacturing cost of our products.

    In the high density CPLD market, we directly compete primarily with Altera and Xilinx, both of whom offer competing products. We also indirectly compete with other PLD suppliers as well as other semiconductor companies who provide non-PLD based logic solutions. Although to date we have not experienced significant competition from companies located outside the United States, such companies may become a more significant competitive factor in the future. Competition may also increase as PLD companies seek to expand our markets. Any such increases in competition could have a material adverse effect on our operating results.

Patents

    We seek to protect our products and wafer fabrication process technologies primarily through patents, trade secrecy measures, copyrights, mask work protection, trademark registrations, licensing restrictions, confidentiality agreements and other approaches designed to protect proprietary information. There can be no assurance that others may not independently develop competitive technology not covered by our intellectual property rights or that measures we take to protect our technology will be effective.

    We hold numerous domestic, European and Asian patents and have patent applications pending in the United States, Asia and Europe. There can be no assurance that pending patent applications or other applications that may be filed will result in issued patents, or that any issued patents will survive challenges to their validity. Although we believe that our patents have value, there can be no assurance that our patents, or any additional patents that may be issued in the future, will provide meaningful protection from competition. We believe that our success will depend primarily upon the technical expertise, experience, creativity and the sales and marketing abilities of our personnel.

    Patent and other proprietary rights infringement claims are common in our industry. There can be no assurance that, with respect to any claim made against us, we could obtain a license on terms or under conditions that would not harm our business.

7

Licenses and Agreements

Seiko Epson/Epson Electronics America

    Epson Electronics America, an affiliated U.S. distributor of Seiko Epson, has agreed to provide us with manufactured wafers in quantities based on six-month rolling forecasts. We have committed to buy certain minimum quantities of wafers per month. Wafers for our products are manufactured in Japan at Seiko Epson's wafer fabrication facilities and are delivered to us by Epson Electronics America. Prices for the wafers obtained from Epson Electronics America are reviewed and adjusted periodically.

    In 1997, we entered into an advance production payment agreement with Seiko Epson and Epson Electronics America under which we agreed to advance approximately $86.0 million, payable upon completion of specific milestones, to Seiko Epson to finance construction of an eight-inch sub-micron semiconductor wafer manufacturing facility. The timing of the payments is related to certain milestones in the development of the facility. Under the terms of the agreement, the advance is to be repaid with semiconductor wafers over a multi-year period. The agreement calls for wafers to be supplied by Seiko Epson through Epson Electronics America pursuant to purchase agreements concluded with Epson Electronics America. Payments of approximately $51.2 million have been made under this agreement.

UMC Group

    In 1995, we entered into a series of agreements with UMC pursuant to which we agreed to join UMC and several other companies to form a separate Taiwanese company, UICC, for the purpose of building and operating an advanced semiconductor manufacturing facility in Taiwan. Under the terms of the agreement, we invested approximately $49.7 million for an approximate 10% equity interest in UICC and the right to purchase a percentage of the facility's wafer production at market prices.

    In 1996, we entered into an agreement with Utek Corporation, a public Taiwanese company in the wafer foundry business that became affiliated with the UMC Group in 1998, pursuant to which we agreed to make a series of equity investments, totaling approximately $17.5 million, in Utek under specific terms. In exchange for these investments we received the right to purchase a percentage of Utek's wafer production.

    On January 3, 2000 UICC and Utek merged into UMC. We currently own approximately 73 million shares of UMC common stock and have retained our capacity rights. Due to contractual and regulatory restrictions, approximately one-third of our UMC shares may not be sold until after January 2002, with the regulatory restrictions expiring between January 2002 and January 2004.

AMD

    In 1999, as part of our acquisition of Vantis, we entered into a series of agreements with AMD to support the continuing operations of Vantis. AMD has agreed to provide us with finished silicon wafers through September 2003 in quantities based either on a rolling six-month or an annual forecast. We have committed to buy certain minimum quantities of wafers and AMD has committed to supply certain quantities of wafers during this period. Wafers for our products are manufactured in the United States at multiple AMD wafer fabrication facilities. Prices for these wafers will be reviewed and adjusted periodically.

    We have also entered into an agreement with AMD pursuant to which we have cross-licensed Vantis patents with AMD patents, having an effective filing date on or before June 15, 1999, related to PLD products. This cross-license was made on a worldwide, non-exclusive and royalty-free basis.

    As part of our acquisition of Vantis Corporation, we have acquired certain third-party license rights held by Vantis prior to the acquisition. Included are rights to use certain Xilinx patents to manufacture, market and sell products.

8

Employees

    As of December 31, 2000 we had 898 full-time employees. We believe that our future success will depend, in part, on our ability to continue to attract and retain highly skilled technical and management personnel. None of our employees is subject to a collective bargaining agreement. We have never experienced a work stoppage and consider our employee relations good.

Item 2. Properties

    Our corporate headquarters are located in three connected buildings we own in Hillsboro, Oregon, comprising a total of approximately 200,000 square feet. We also own a 13,000 square foot research and development facility and approximately 6,000 square feet of dormitory facilities in Shanghai, China. We lease a 133,000 square foot facility in San Jose, California (through 2008), a 40,000 square foot product development facility in Austin, Texas (through 2004) and a 7,000 square foot product development facility in Colorado Springs, Colorado (through 2004). We also lease, on a short-term basis, office facilities for our product development facility in the United Kingdom and for our domestic and international sales offices. Additionally, we lease a 80,000 square foot facility in Sunnyvale, California (through 2006) which has been subleased to a third party through the end of the lease term.

Item 3. Legal Proceedings

    In connection with our acquisition of Vantis, we have agreed to assume both the claims against Altera and the claims by Altera against AMD in the case captioned Advanced Micro Devices, Inc. v. Altera Corporation (Case No. C-94-20567-RMW) proceeding in the United States District Court for the Northern District of California. This litigation, which began in 1994, involves multiple claims and counterclaims for patent infringement relating to Vantis and Altera programmable logic devices and both parties are seeking damages and injunctive relief.

    In April 1999, the United States Court of Appeals for the Federal Circuit reversed earlier jury and District Court decisions and held that Altera is not licensed to the eight AMD patents-in-suit. These eight AMD patents were subsequently assigned to Vantis. Also in April 1999, following the decision of the Court of Appeals, Altera filed a petition for rehearing. In June 1999, the Court of Appeals denied Altera's petition for rehearing.

    On May 31, 2000, Altera Corporation filed a complaint against us in United States District Court for the Northern District of California, alleging infringement of certain Altera patents by unspecified Lattice products. On June 22, 2000, we answered Altera's complaint denying any infringement by Lattice, and simultaneously brought a series of counterclaims alleging infringement by Altera of certain Lattice patents.

    Although there can be no assurance as to the results of litigation, based upon information presently known to management, we do not believe that the ultimate resolution of lawsuits will have a material adverse effect on our financial position, cash flows or results of operations. The foregoing statement constitutes a forward-looking statement and the actual results may differ materially depending on a number of factors, including new court decisions and additional counterclaims made by other parties to such litigation. Except as described above, we are not currently a party to any material legal proceedings.

Item 4. Submission of Matters to a Vote of Security Holders

    Not applicable.

9

Item 4(a). Executive Officers of the Registrant

    The following table sets forth certain information regarding our executive officers and directors:

    Cyrus Y. Tsui joined Lattice in September 1988 as President, Chief Executive Officer and Director, and in March 1991 was named Chairman of the Board. From 1987 until he joined, Mr. Tsui was Corporate Vice President and General Manager of the Programmable Logic Division of AMD. He was Vice President and General Manager of the Commercial Products Divisions of Monolithic Memories Incorporated (MMI) from 1983 until its merger with AMD in 1987. Mr. Tsui has held technical and managerial positions in the semiconductor industry for over 30 years. He has worked in the programmable logic industry since its inception.

    Steven A. Laub joined Lattice in June 1990 as Vice President and General Manager. He was elected Senior Vice President and Chief Operating Officer in August 1996.

    Stephen A. Skaggs joined Lattice in December 1992 as Director, Corporate Development. He was elected Senior Vice President, Chief Financial Officer and Secretary in August 1996.

    Frank J. Barone joined Lattice in June 1999 as a Corporate Vice President as a result of the Vantis acquisition. From September 1997 until he joined, Mr. Barone was Chief Operating Officer of Vantis. Prior thereto, Mr. Barone held various technical and managerial positions at AMD. He has worked in the programmable logic industry since 1978.

    Stephen M. Donovan joined Lattice in October 1989 and has served as Director of Marketing and Director of International Sales. He was elected Vice President, International Sales in August 1993. He

10

was elected Corporate Vice President, Sales, in May 1998. Mr. Donovan has worked in the programmable logic industry since 1982.

    Jonathan K. Yu joined Lattice in February 1992 as Vice President, Operations. He was elected Corporate Vice President, Business Development in August 1996. Mr. Yu has held technical and managerial positions in the semiconductor industry for over 30 years.

    Martin R. Baker joined Lattice in January 1997 as Vice President and General Counsel. From 1991 until he joined, Mr. Baker held legal positions with Altera Corporation.

    Randy D. Baker joined Lattice in April 1985 as Manager, Manufacturing and was promoted in 1988 to Director, Manufacturing. He was elected Vice President, Manufacturing in August 1996.

    Albert L. Chan joined Lattice in May 1989 as California Design Center Manager and was promoted in 1991 to Director, California Product Development Center. He was elected Vice President, California Product Development in August 1993. He was elected Vice President and General Manager, Lattice Silicon Valley, in August 1997. Mr. Chan has worked in the programmable logic industry since 1983.

    Thomas J. Kingzett joined Lattice in July 1992 as Director, Reliability and Quality Assurance. He was elected Vice President, Reliability and Quality Assurance in May 1998. Mr. Kingzett has worked in the semiconductor industry for over 25 years.

    Stanley J. Kopec joined Lattice in August 1992 as Director, Marketing. He was elected Vice President, Corporate Marketing in May 1998. Mr. Kopec has worked in the programmable logic industry since 1985.

    Andrew D. Robin joined Lattice in June 1999 as Vice President, New Venture Business as a result of the Vantis acquisition. From March 1998 until he joined, Mr. Robin was Vice President, Marketing at Vantis. Prior thereto, Mr. Robin held various marketing and managerial positions at AMD and MMI. Mr. Robin has worked in the programmable logic industry since 1984.

    Rodney F. Sloss joined Lattice in May 1994 as Vice President, Finance.

    Kenneth K. Yu joined Lattice in January 1991 as Director of Process Technology. He has served as Managing Director, Lattice Asia since November 1992 and was elected Vice President, Lattice Asia in August 1993. Mr. Yu has held technical and managerial positions in the semiconductor industry for over 25 years.

    Mark O. Hatfield has been a member of our board of directors since 1997. Mr. Hatfield is a former U.S. Senator from Oregon.

    Daniel S. Hauer has been a member of our board of directors since 1987. Mr. Hauer is the former Chairman and Chief Executive Officer of Epson Electronics America.

    Soo Boon Koh joined our board of directors in August 2000. Ms. Koh is the managing partner of iGlobe Partners Fund LP, a venture capital fund located in Singapore and the United States.

    Harry A. Merlo has been a member of our board of directors since 1983. Mr. Merlo is the President of Merlo Corporation and is the former President and Chairman of Louisiana-Pacific Corporation.

    Larry W. Sonsini has been a member of our board of directors since 1991. Mr. Sonsini is Chairman and CEO of Wilson Sonsini Goodrich & Rosati, Professional Corporation, a law firm based in Palo Alto, California.

11

PART II

Item 5. Market for the Registrant's Common Stock and Related Stockholder Matters.

    Our common stock is traded on the over-the-counter market and prices are quoted on the Nasdaq National Market under the symbol "LSCC". The following table sets forth the low and high sale prices for our common stock for the last two fiscal years and for the period since December 31, 2000. On March 22, 2001, the last reported sale price of our common stock was $21.25. As of March 15, 2001, we had approximately 426 stockholders of record.

    All share amounts have been adjusted retroactively to reflect our two-for-one stock splits effected in the form of stock dividends of one share of common stock for each share of our outstanding common stock and paid on September 16, 1999 and October 11, 2000.

    The payment of dividends on our common stock is within the discretion of our Board of Directors. We intend to retain earnings to finance the growth of our business. We have not paid cash dividends and our Board of Directors does not expect to declare a cash dividend in the near future.

Item 6. Selected Financial Data.

    The section entitled "Selected Financial Data" in our 2000 Annual Report to Stockholders at page 17 is incorporated herein by reference.

Item 7. Management's Discussion and Analysis of Financial Condition and Results of Operations.

    This report contains forward-looking statements within the meaning of Section 27A of the Securities Act of 1933, as amended, and Section 21E of the Securities Exchange Act of 1934, as amended. Actual results could differ materially from those projected in the forward-looking statements as a result of the factors set forth in the section entitled "Factors Affecting Future Results" and elsewhere in this report.

    Lattice Semiconductor Corporation designs, develops and markets high performance programmable logic devices, or PLDs, and related software. Programmable logic devices are widely-used semiconductor components that can be configured by the end customer as specific logic circuits, and enable the end customer to shorten design cycle times and reduce development costs. Our end customers are primarily original equipment manufacturers in the markets of data communications and telecommunications, as well as computing, industrial and military systems.

12

    In 1999, we acquired Vantis Corporation, the programmable logic device subsidiary of Advanced Micro Devices. This acquisition has increased our share of the PLD market, accelerated development of new products and technologies and expanded our penetration into new and existing customers.

    As indicated in our Consolidated Financial Statements, 2000 is a twelve month fiscal period, as compared to the nine month fiscal period 1999 and twelve month fiscal year 1999.

Results of Operations

    The following table sets forth, for the periods indicated, the percentage of revenue represented by selected items reflected in our Consolidated Statement of Operations:

Acquisition of Vantis.  As discussed in more detail in note 4 to our Consolidated Financial Statements, we completed the acquisition of Vantis Corporation ("Vantis") from AMD on June 15, 1999. We paid approximately $500.1 million in cash for all of the outstanding capital stock of Vantis, plus $10.8 million in direct acquisition costs, $5.4 million of accrued pre-acquistion contingencies, $8.3 million of accrued exit costs, and assumed certain liabilities of $34.5 million related to the Vantis business. In addition, we exchanged Lattice stock options for all of the outstanding stock options under the former Vantis employee stock plans with a calculated Black-Scholes value of $24.0 million. The total purchase price for Vantis was $583.1 million. The purchase price was allocated to the estimated fair value of assets acquired and liabilities assumed based on an independent appraisal and management estimates. In process research and development (IPR&D) costs were appraised at $89 million at the acquisition date using a methodology consistent with current views of the staff of the SEC. These IPR&D costs were charged to operations on the acquisition date. Remaining intangible asset costs of $422.6 million, at the acquisition date, are being amortized to operations over five years using the straight-line method.

    The purchase was financed using a combination of cash reserves and a new credit facility bearing interest at adjustable rates. The new credit facility was replaced with Convertible Notes in November 1999 (see note 8 to the Consolidated Financial Statements). We have taken certain actions to integrate the Vantis operations and, in certain instances, to consolidate duplicative operations.

13

Revenue.  Revenue was $567.8 million in 2000, an increase of 111% from fiscal period 1999. Fiscal period 1999 revenue of $269.7 million represented an increase of 35% from the $200.1 million recorded in fiscal year 1999.

    In addition to our acquisition of Vantis, this increase in revenue is primarily attributable to increased sales of high density products, particularly our new 3.3 volt high density products, in all geographic regions. Revenue from the sale of high-density products represented 76%, 68% and 69% of total revenue for 2000, fiscal period 1999 and fiscal year 1999, respectively. Additionally, 2000 was a twelve month fiscal period, as opposed to the nine month fiscal period 1999. Fiscal period 1999 revenue, when compared to fiscal year 1999 revenue, was positively impacted by increased demand from Asia in conjunction with that region's economic recovery.

    Our sales by major geographic region were as follows:

    Revenue from export sales as a percentage of total revenue was approximately 57% for 2000, 53% for fiscal period 1999 and 50% for fiscal year 1999. We expect export sales to continue to represent a significant portion of revenue.

    The average selling price of our products increased in 2000 as compared to fiscal period 1999, but decreased slightly in fiscal period 1999 as compared to fiscal year 1999. This fluctuation in overall average selling price is due primarily to product mix changes and increased sales of high density products. Although selling prices of mature products generally decline over time, this decline is at times offset by higher selling prices of new products. Our ability to maintain or increase the level of our average selling price is dependent on the continued development, introduction and market acceptance of new products. See "Factors Affecting Future Results".

    In March 2001, we announced that we expected a significant sequential decline in revenue in the first quarter of 2001. We believe this shortfall is the result of a general decline in PLD consumption within the communications and computing end markets. The extent of this decline and whether this decline will continue or accelerate is not known at this time.

    Gross Margin.  Our gross margin was 62% for 2000, 60% for fiscal period 1999 and 61% for fiscal year 1999. The gross margin improvement in 2000 as compared to fiscal period 1999 is primarily due to continued reductions in our manufacturing costs and improvements in our product mix. The gross margin decline in fiscal period 1999 as compared to fiscal year 1999 is attributable to our acquisition of Vantis. The decline was partially offset by an improvement in product mix and reductions in our manufacturing costs. Reductions in manufacturing costs resulted primarily from yield improvements, migration of products to more advanced technologies and smaller die sizes.

    Research and Development.  Research and development expense was $77.1 million in 2000, $45.9 million in fiscal period 1999 and $33.2 million in fiscal year 1999. In addition to our acquisition of Vantis, spending increases resulted primarily from the increased development of new products.

14

Additionally, 2000 was a twelve month fiscal period, as opposed to the nine month fiscal period 1999. We believe that a continued commitment to research and development is essential in order to maintain product leadership in our existing product families and provide innovative new product offerings, and therefore we expect to continue to make significant future investments in research and development.

Selling, General and Administrative.  Selling, general and administrative expense was $81.1 million in 2000, $50.7 million in fiscal period 1999 and $36.8 million in fiscal year 1999. Increased expenses were primarily due to increased variable costs associated with higher revenue levels and our Vantis acquisition. Additionally, 2000 was a twelve month fiscal period, as opposed to the nine month fiscal period 1999.

In-Process Research and Development.  In-process research and development costs of approximately $89.0 million were incurred on June 15, 1999 in connection with our acquisition of Vantis, and are further described in note 4 to our Consolidated Financial Statements.

Amortization of Intangible Assets.  Amortization of intangible assets acquired in the Vantis acquisition was $81.9 million in 2000 and $45.8 million for fiscal period 1999. The increase in amortization for 2000 as compared to 1999 was primarily due to a full year of amortization in 2000 as opposed to approximately 6.5 months (June 15, 1999 acquisition date through December 31, 1999) in fiscal period 1999. The estimated weighted average useful life of the intangible assets for current technology, assembled workforce, customer lists, trademarks, patents and residual goodwill, created as a result of the acquisition, is approximately five years.

Gain on Appreciation of Foundry Investments.  This gain on appreciation of foundry investments in 2000 was recorded on January 3, 2000. It represents appreciation of equity investments made in two Taiwanese companies, UICC and Utek, as described in note 5 to our Consolidated Financial Statements.

Interest income.  Interest income was $16.2 million in 2000, an increase of 167% as compared to fiscal period 1999. This increase was attributable to increased cash balances generated from our follow-on stock offering, completed in July 2000, a twelve month fiscal period in 2000 as opposed to the nine month fiscal period 1999, and cash generated from operations and exercises of stock options. Fiscal period 1999 interest income was $6.1 million, a decrease of 46% as compared to fiscal year 1999. This resulted primarily from lower cash and investment balances in conjunction with our Vantis acquisition, and a nine month fiscal period 1999 as compared to the twelve month fiscal year 1999.

Interest expense.  Interest expense was approximately $14.0 million in 2000, an increase of 44% as compared to fiscal period 1999. Substantially all interest expense resulted from the debt issued to partially fund our Vantis acquisition. Acquisition-related debt was outstanding for all of 2000, but only for six and one-half months in fiscal period 1999.

Provision for Income Taxes.  Our effective tax rate was 35.9% in 2000, as compared to a benefit for income taxes of 37.6% for fiscal period 1999 and a 32.5% effective tax rate for fiscal year 1999. The benefit for income taxes for fiscal period 1999 was attributable to the tax effect of the In-process Research and Development recognized in conjunction with our Vantis acquisition. The effective tax rates for 2000 and fiscal year 1999 were lower than the statutory rate primarily because of tax exempt investment income and tax credits.

Extraordinary item, net of income taxes.  The extraordinary item, net of income taxes, in fiscal period 1999 represents the writeoff of unamortized loan fees related to the credit facility repaid in conjunction with the re-financing of our acquisition of Vantis.

15

Factors Affecting Future Results

    Notwithstanding any objectives, projections, estimates and other forward-looking statements contained in this Annual Report, our future operating results will continue to be subject to quarterly variations based on a wide variety of risks. The following risks, and potentially other risks, may cause our actual results to differ materially from those expressed in our forward-looking statements:

The cyclical nature of the semiconductor industry may limit our ability to maintain or increase revenue and profit levels during industry downturns.

    The semiconductor industry is highly cyclical, to a greater extent than other less dynamic or less technology-driven industries. Currently, the industry is undergoing a cyclical downturn. In the past, our financial performance has been negatively affected by significant downturns in the semiconductor industry as a result of:

•

the cyclical nature of the demand for the products of semiconductor customers;



•

general reductions in inventory levels by customers;



•

excess production capacity; and



•

accelerated declines in average selling prices.

When these or other conditions in the semiconductor industry occur, there is likely to be an adverse effect on our operating results.

We may be unsuccessful in defining, developing or selling new products required to maintain or expand our business.

    As a semiconductor company, we operate in a dynamic environment marked by rapid product obsolescence. Our future success depends on our ability to introduce new or improved products that meet customer needs while achieving acceptable margins. If we fail to introduce these new products in a timely manner or these products fail to achieve market acceptance, our operating results would be harmed.

    The introduction of new products in a dynamic market environment presents significant business challenges. Product development commitments and expenditures must be made well in advance of product sales. The success of a new product depends on accurate forecasts of long-term market demand and future technology developments.

    Our future revenue growth is dependent on market acceptance of our new product families and the continued market acceptance of our software development tools. The success of these products is dependent on a variety of specific technical factors including:

•

successful product definition;



•

timely and efficient completion of product design;



•

timely and efficient implementation of wafer manufacturing and assembly processes;



•

product performance; and



•

the quality and reliability of the product.

If, due to these or other factors, our new products do not achieve market acceptance, our operating results would be harmed.

16

Our future quarterly operating results may fluctuate and therefore may fail to meet expectations.

    Our quarterly operating results have fluctuated and may continue to fluctuate. Consequently, our operating results may fail to meet the expectations of analysts and investors. As a result of industry conditions and the following specific factors, our quarterly operating results are more likely to fluctuate and are more difficult to predict than a typical non-technology company of our size and maturity:

•

general economic conditions in the countries where we sell our products;



•

the timing of our and our competitors' new product introductions;



•

product obsolescence;



•

excessive inventory accumulation by our end customers;



•

the scheduling, rescheduling and cancellation of large orders by our customers;



•

the cyclical nature of demand for our customers' products;



•

our ability to develop new process technologies and achieve volume production at the new fabs of Seiko Epson, UMC or at other foundries;



•

changes in manufacturing yields;



•

adverse movements in exchange rates, interest rates or tax rates; and



•

the availability of adequate supply commitments from our wafer foundries and assembly and test subcontractors.

As a result of these factors, our past financial results are not necessarily a good predictor of our future results.

Our stock price may continue to experience large short-term fluctuations.

    In recent years, the price of our common stock has fluctuated greatly. These price fluctuations have been rapid and severe and have left investors little time to react. The price of our common stock may continue to fluctuate greatly in the future due to a variety of company specific factors, including:

•

quarter-to-quarter variations in our operating results;



•

shortfalls in revenue or earnings from levels expected by securities analysts; and



•

announcements of technological innovations or new products by other companies.

Our wafer supply may be interrupted or reduced, which may result in a shortage of finished products available for sale.

    We do not manufacture finished silicon wafers. Currently, all of our silicon wafers are manufactured by Seiko Epson in Japan, AMD in the United States and UMC in Taiwan. If Seiko Epson, through its U.S. affiliate Epson Electronics America, AMD or UMC significantly interrupts or reduces our wafer supply, our operating results could be harmed.

    In the past, we have experienced delays in obtaining wafers and in securing supply commitments from our foundries. At present, we anticipate that our supply commitments are adequate. However, these existing supply commitments may not be sufficient for us to satisfy customer demand in future periods. Additionally, notwithstanding our supply commitments, we may still have difficulty in obtaining wafer deliveries consistent with the supply commitments. We negotiate wafer prices and supply commitments from our suppliers on at least an annual basis. If any of Seiko Epson, Epson Electronics America, AMD or UMC were to reduce its supply commitment or increases its wafer prices, and we cannot find alternative sources of wafer supply, our operating results could be harmed.

17

    Many other factors that could disrupt our wafer supply are beyond our control. Since worldwide manufacturing capacity for silicon wafers is limited and inelastic, we could be harmed by significant industry-wide increases in overall wafer demand or interruptions in wafer supply. Additionally, a future disruption of Seiko Epson's, AMD's or UMC's foundry operations as a result of a fire, earthquake or other natural disaster could disrupt our wafer supply and could harm our operating results.

Our products may not be competitive if we are unsuccessful in migrating our manufacturing processes to more advanced technologies.

    To develop new products and maintain the competitiveness of existing products, we need to migrate to more advanced wafer manufacturing processes that use larger wafer sizes and smaller device geometries. We also may need to use additional foundries. Because we depend upon foundries to provide their facilities and support for our process technology development, we may experience delays in the availability of advanced wafer manufacturing process technologies at existing or new wafer fabrication facilities. As a result, volume production of our advanced E²CMOS process technologies at the new fabs of Seiko Epson, UMC or future foundries may not be achieved. This could harm our operating results.

If our foundry partners experience quality or yield problems, we may face a shortage of finished products available for sale.

    We depend on our foundries to deliver reliable silicon wafers with acceptable yields in a timely manner. As is common in our industry, we have experienced wafer yield problems and delivery delays. If our foundries are unable to produce silicon wafers that meet our specifications, with acceptable yields, for a prolonged period, our operating results could be harmed.

    Substantially all of our revenue is derived from products based on a specialized silicon wafer manufacturing process technology called E²CMOS®. The reliable manufacture of high performance E²CMOS semiconductor wafers is a complicated and technically demanding process requiring:

•

a high degree of technical skill;



•

state-of-the-art equipment;



•

the absence of defects in the masks used to print circuits on a wafer;



•

the elimination of minute impurities and errors in each step of the fabrication process; and



•

effective cooperation between the wafer supplier and the circuit designer.

As a result, our foundries may experience difficulties in achieving acceptable quality and yield levels when manufacturing our silicon wafers.

If our assembly and test subcontractors experience quality or yield problems, we may face a shortage of finished products available for sale.

    We rely on subcontractors to assemble and test our devices with acceptable quality and yield levels. As is common in our industry, we have experienced quality and yield problems in the past. If we experience prolonged quality or yield problems in the future, our operating results could be harmed.

    The majority of our revenue is derived from semiconductor devices assembled in advanced packages. The assembly of advanced packages is a complex process requiring:

•

a high degree of technical skill;



•

state-of-the-art equipment;



•

the absence of defects in lead frames used to attach semiconductor devices to the package;

18

•

the elimination of raw material impurities and errors in each step of the process; and



•

effective cooperation between the assembly subcontractor and the device manufacturer.

As a result, our subcontractors may experience difficulties in achieving acceptable quality and yield levels when assembling and testing our semiconductor devices.

Deterioration of conditions in Asia may disrupt our existing supply arrangements and result in a shortage of finished products available for sale.

    Two of our three silicon wafer suppliers operate fabs located in Asia. Our finished silicon wafers are assembled and tested by independent subcontractors located in Hong Kong, Malaysia, the Philippines, South Korea, Taiwan and Thailand. A prolonged interruption in our supply from any of these subcontractors could harm our operating results.

    Economic, financial, social and political conditions in Asia have historically been volatile. Financial difficulties, governmental actions or restrictions, prolonged work stoppages or any other difficulties experienced by our suppliers may disrupt our supply and could harm our operating results.

    Our wafer purchases from Seiko Epson are denominated in Japanese yen. The value of the dollar with respect to the yen fluctuates. Substantial deterioration of dollar-yen exchange rates could harm our operating results.

Export sales account for a substantial portion of our revenues and may decline in the future due to economic and governmental uncertainties.

    Our export sales are affected by unique risks frequently associated with foreign economies including:

•

changes in local economic conditions;



•

exchange rate volatility;



•

governmental controls and trade restrictions;



•

export license requirements and restrictions on the export of technology;



•

political instability;



•

changes in tax rates, tariffs or freight rates;



•

interruptions in air transportation; and



•

difficulties in staffing and managing foreign sales offices.

    For example, our export sales have historically been affected by regional economic crises. Significant changes in the economic climate in the foreign countries where we derive our export sales could harm our operating results.

We may not be able to successfully compete in the highly competitive semiconductor industry.

    The semiconductor industry is intensely competitive and many of our direct and indirect competitors have substantially greater financial, technological, manufacturing, marketing and sales resources. If we are unable to compete successfully in this environment, our future results will be adversely affected.

    The current level of competition in the programmable logic market is high and may increase as our market expands. We currently compete directly with companies that have licensed our products and technology or have developed similar products. We also compete indirectly with numerous

19

semiconductor companies that offer products and solutions based on alternative technologies. These direct and indirect competitors are established multinational semiconductor companies as well as emerging companies. We also may experience significant competition from foreign companies in the future.

We may fail to retain or attract the specialized technical and management personnel required to successfully operate our business.

    To a greater degree than most non-technology companies or larger technology companies, our future success depends on our ability to attract and retain highly qualified technical and management personnel. As a mid-sized company, we are particularly dependent on a relatively small group of key employees. Competition for skilled technical and management employees is intense within our industry. As a result, we may not be able to retain our existing key technical and management personnel. In addition, we may not be able to attract additional qualified employees in the future. If we are unable to retain existing key employees or are unable to hire new qualified employees, our operating results could be adversely affected.

If we are unable to adequately protect our intellectual property rights, our financial results and competitive position may suffer.

    Our success depends in part on our proprietary technology. However, we may fail to adequately protect this technology. As a result, we may lose our competitive position or face significant expense to protect or enforce our intellectual property rights. We intend to continue to protect our proprietary technology through patents, copyrights and trade secrets. Despite this intention, we may not be successful in achieving adequate protection. Claims allowed on any of our patents may not be sufficiently broad to protect our technology. Patents issued to us also may be challenged, invalidated or circumvented. Finally, our competitors may develop similar technology independently.

    Companies in the semiconductor industry vigorously pursue their intellectual property rights. If we become involved in protracted intellectual property disputes or litigation we may utilize substantial financial and management resources, which could have an adverse effect on our operating results. We may also be subject to future intellectual property claims or judgements. If these were to occur, we may not be able to obtain a license on favorable terms or without our operating results being adversely affected.

Liquidity and Capital Resources

    As of December 31, 2000, our principal source of liquidity was $535.4 million of cash and short-term investments, an increase of $321.3 million from the balance of $214.1 million at December 31, 1999. This increase was primarily due to the generation of approximately $210 million in net proceeds from our follow-on stock offering in July 2000, as well as cash generated from operations and exercises of stock options. Working capital increased to $552.2 million at December 31, 2000 from $152.8 million at December 31, 1999. This increase in working capital was primarily due to the increase in cash and short term investments. During 2000, we generated approximately $94.3 million of cash and cash equivalents from our operations compared with $80.9 million during the nine months of fiscal period 1999.

    Accounts receivable at December 31, 2000 increased by $16.0 million, or 48%, as compared to the balance at December 31, 1999. This increase was primarily due to increased product shipments and revenue levels in comparison to fiscal period 1999. Inventories increased by $33.5 million, or 129%, as compared to the balance at December 31, 1999 primarily due to increased production in response to the higher revenue levels. Prepaid expenses and other current assets increased by $13.2 million, or 131% as compared to the balance at December 31, 1999, primarily due to a $10 million increase in the

20

current portion of wafer supply advances. Current deferred income taxes increased $19.4 million, or 65%, as compared to the balance at December 31, 1999, primarily due to the increase in deferred income for sales to distributors which is recognized currently for income tax purposes, and to a lesser extent the timing of deductions for certain expenses and allowances. Foundry investments increased by $59.1 million, or approximately 45%, as compared to the balance at December 31, 1999. This was primarily due to the $92.1 million after-tax gain recorded in the first quarter of 2000 representing the appreciation of our foundry investments, offset by a $47.9 million unrealized loss (recorded in Other Comprehensive Loss) on the unrestricted portion of these investments due to subsequent market depreciation. Net property and equipment increased by $8.9 million, or 15%, as compared to the balance at December 31, 1999 primarily due to capital expenditures. Intangible assets, net, decreased by $86.8 million, or 23% as compared to the balance at December 31, 1999 due primarily to goodwill and other intangibles amortization. Net non-current deferred tax assets decreased $4.5 million versus the balance at December 31, 1999. This decrease was primarily due to the following factors: (1) a $19.0 million increase in non-current deferred tax assets due to timing differences between book and tax recognition of future income tax benefits to be derived from the amortization of intangible assets and the IPR&D charges, (2) an increase in non-current deferred tax liabilities of $27.9 million recorded in conjunction with the gain and subsequent unrealized loss recorded on our foundry investments as discussed above, and (3) other timing differences between book and tax recognition of future income tax benefits.

    Accounts payable and accrued expenses decreased by $10.5 million, or 12%, as compared to the balance at December 31, 1999 due primarily to liquidation of liabilities recorded in conjunction with our acquisition of Vantis in June 1999. Deferred income increased by $13.0 million, or 29%, as compared to the balance at December 31, 1999, due primarily to increased billings to distributors associated with higher revenue levels in 2000.

    On October 28, 1999, we issued $260 million in 4³/4% convertible subordinated notes due on November 1, 2006. These notes require that we pay interest semi-annually on May 1 and November 1. Holders of these notes may convert them into shares of our common stock at any time on or before November 1, 2006, at a conversion price of $20.72 per share, subject to adjustment in certain events. Beginning on November 6, 2002 and ending on October 31, 2003, we may redeem the notes in whole or in part at a redemption price of 102.71% of the principal amount. In the subsequent three twelve-month periods, the redemption price declines to 102.04%, 101.36% and 100.68% of principal, respectively. The notes are subordinated in right of payment to all of our senior indebtedness, and are subordinated to all liabilities of our subsidiaries. At December 31, 2000, we had no senior indebtedness and our subsidiaries had $3.6 million of other liabilities. Issuance costs relative to the convertible subordinated notes are included in Other Assets and aggregated approximately $6.9 million and are being amortized to expense over the life of the notes. Accumulated amortization amounted to approximately $2.1 million at December 31, 2000.

    On June 15, 1999, we entered into a credit agreement with a group of lenders and ABN AMRO Bank N.V. ("ABN AMRO") as administrative agent for the lender group. The credit agreement consisted of two credit facilities: a $60 million unsecured revolving credit facility ("Revolver"), and a $220 million unsecured reducing term loan ("Term Loan"), both expiring and due on June 30, 2002. On June 15, 1999, we borrowed $220 million under the Term Loan and approximately $33 million under the Revolver. The $33 million Revolver was repaid in full during the third calendar quarter of 1999. In conjunction with the issuance of the convertible subordinated notes, we repaid the $220 million Term Loan in full during the fourth calendar quarter of fiscal 1999. Remaining unamortized loan fees at the time of repayment, aggregating approximately $2.6 million ($1.665 million net of income taxes or a charge of $0.02 for basic and diluted earnings per share), were written off and are reflected in our Consolidated Statement of Operations as an Extraordinary Item, Net of Income Taxes.

21

    Capital expenditures were approximately $25.9 million, $15.7 million and $18.4 million for 2000, fiscal period 1999, and fiscal year 1999, respectively. We expect to spend approximately $20 million to $25 million for the fiscal year ending December 31, 2001.

    In March 1997, we entered into an advance payment production agreement with Seiko Epson and its affiliated U.S. distributor, Epson Electronics America, under which we agreed to advance approximately $86 million, payable upon completion of specific milestones, to Seiko Epson to finance construction of an eight-inch sub-micron wafer manufacturing facility. Under the terms of the agreement, the advance is to be repaid with semiconductor wafers over a multi-year period. The agreement calls for wafers to be supplied by Seiko Epson through Epson Electronics America, pursuant to purchase agreements with Epson Electronics America. Payments of approximately $51.2 million have been made under this agreement.

    In 1995, we entered into a series of agreements with UMC, pursuant to which we agreed to join UMC and several other companies to form a separate Taiwanese company, UICC, for the purpose of building and operating an advanced semiconductor manufacturing facility in Taiwan. Under the terms of the agreements, we invested approximately $49.7 million for an approximate 10% equity interest in UICC and the right to receive a percentage of the facility's wafer production at market prices.

    In 1996, we entered into an agreement with Utek, a public Taiwanese company in the wafer foundry business that became affiliated with the UMC Group in 1998, pursuant to which we agreed to make a series of equity investments in Utek under specific terms. In exchange for these investments we received the right to purchase a percentage of Utek's wafer production. Under this agreement, we invested approximately $17.5 million in three separate installments.

    On January 3, 2000, UICC and Utek merged into UMC. We own approximately 73 million shares of UMC common stock and have retained our capacity rights. Due to contractual and regulatory restrictions, approximately one-third of our shares may not be sold until after January 2002, with the regulatory restrictions expiring between January 2002 and January 2004.

    In June 1999, as part of our acquisition of Vantis, we entered into a series of agreements with AMD to support the continuing operations of Vantis. AMD has agreed to provide us with finished silicon wafers through September 2003 in quantities based either on a rolling six-month or an annual forecast. We have committed to buy certain minimum quantities of wafers and AMD has committed to supply certain quantities of wafers during this period. Wafers for our products are manufactured in the United States at multiple AMD wafer fabrication facilities. Prices for these wafers will be reviewed and adjusted periodically.

    We believe that our existing liquid resources, expected cash generated from operations and existing credit facilities combined with our ability to borrow additional funds will be adequate to meet our operating and capital requirements and obligations for the next 12 months.

    In an effort to secure additional wafer supply, we may from time to time consider various financial arrangements including joint ventures, equity investments, advance purchase payments, loans, or similar arrangements with independent wafer manufacturers in exchange for committed wafer capacity. To the extent that we pursue any such additional financing arrangements, additional debt or equity financing may be required. We may in the future seek new or additional sources of funding. There can be no assurance that such additional financing will be available when needed or, if available, will be on favorable terms. Any future equity financing will decrease existing stockholders' equity percentage ownership and may, depending on the price at which the equity is sold, result in dilution.

Item 7(a) Quantitative and Qualitative Disclosures About Market Risk.

    As of December 31, 2000 and December 31, 1999 our investment portfolio consisted of fixed income securities of $507.3 million and $182.1 million, respectively. As with all fixed income

22

instruments, these securities are subject to interest rate risk and will decline in value if market interest rates increase. If market rates were to increase immediately and uniformly by 10% from levels as of December 31, 2000 and December 31, 1999, the decline in the fair value of the portfolio would not be material. Further, we have the ability to hold our fixed income investments until maturity and, therefore, we would not expect to recognize such an adverse impact in our income or cash flows.

    We have international subsidiary and branch operations. Additionally, a portion of our silicon wafer purchases are denominated in Japanese yen. We therefore are subject to foreign currency rate exposure. To mitigate rate exposure with respect to yen-denominated wafer purchases, we maintain yen-denominated bank accounts and bill our Japanese customers in yen. The yen bank deposits are utilized to hedge yen-denominated wafer purchases against specific and firm wafer purchases. If the foreign currency rates fluctuate by 10% from rates at December 31, 2000 and December 31, 1999, the effect on our consolidated financial statements would not be material. However, there can be no assurance that there will not be a material impact in the future.

    We are exposed to equity price risk due to our equity investment in UMC (see note 5 to our Consolidated Financial Statements). Neither a 10% increase nor a further 10% decrease in equity price related to this investment would have a material impact on our Consolidated Financial Statements. However, there can be no assurance that there will not be a material impact in the future.

Item 8. Financial Statements and Supplementary Data.

    The section entitled "Consolidated Financial Statements" on pages 18 through 31 in our 2000 Annual Report to Stockholders is incorporated herein by reference.

Consolidated Financial Statement Schedules:

Item 9. Changes in and Disagreements with Accountants On Accounting and Financial Disclosure.

    Not applicable.

    With the exception of the information expressly incorporated by reference from the Annual Report to Stockholders into Parts II and IV of this Form 10-K, the Company's Annual Report to Stockholders is not to be deemed filed as part of this Report.

PART III

    Certain information required by Part III is omitted from this Report in that the Company will file its definitive proxy statement for the Annual Meeting of Stockholders to be held on May 1, 2001, pursuant to Regulation 14A of the Securities Exchange Act of 1934 (the "Proxy Statement"), not later than 120 days after the end of the fiscal year covered by this Report, and certain information included in the Proxy Statement is incorporated herein by reference. With the exception of the information expressly incorporated by reference from the Proxy Statement, the Company's Proxy Statement is not to be deemed filed as a part of this report.

Item 10. Directors and Executive Officers of the Registrant.

    The caption entitled "Proposal 1: Election of Directors" in the Company's Proxy Statement is incorporated herein by reference. Information with respect to executive officers of the Company is included under Item 4(a) of Part I of this Report and is incorporated herein by reference.

23

Item 11. Executive Compensation.

    The caption entitled "Proposal 1: Election of Directors," "Executive Compensation," "Options Granted and Options Exercised in the Last Fiscal Year" and "Comparison of Total Cumulative Stockholder Return" in the Company's Proxy Statement is incorporated herein by reference.

Item 12. Security Ownership of Certain Beneficial Owners and Management.

    The caption entitled "Security Ownership of Certain Beneficial Owners and Management" in the Company's Proxy Statement is incorporated herein by reference.

Item 13. Certain Relationships and Related Transactions.

    The caption entitled "Proposal 1: Election of Directors—Transactions with Management" in the Company's Proxy Statement is incorporated herein by reference.

PART IV

Item 14. Exhibits, Financial Statement Schedules and Reports on Form 8-K.

(a)(1) and (2) Financial Statements and Financial Statement Schedules.

    The information required by this Item is included under Item 8 of this Report.

(a)(3) EXHIBITS.

24

25

(1)

Pursuant to Rule 24b-2 under the Securities Exchange Act of 1934, confidential treatment has been granted to portions of this exhibit, which portions have been deleted and filed separately with the Securities and Exchange Commission.

*

Management contract or compensatory plan or arrangement required to be filed as an Exhibit to this Annual Report on Form 10-K pursuant to Item14(c) thereof.

(b)

No reports on Form 8-K were filed during the last quarter of 2000.

(c)

See (a)(3) above.

(d)

See (a)(1) and (2) above.

26

SIGNATURES

    Pursuant to the requirements of Section 13 or 15(d) of the Securities Exchange Act of 1934, the Registrant has duly caused this Report to be signed on its behalf by the undersigned, thereunto duly authorized, in the City of Hillsboro, State of Oregon, on the 23rd of March, 2001.

POWER OF ATTORNEY

    KNOW ALL PERSONS BY THESE PRESENTS, that each person whose signature appears below constitutes and appoints Cyrus Y. Tsui and Stephen A. Skaggs, jointly and severally, his attorneys-in-fact, each with the power of substitution, for him in any and all capacities, to sign any amendments to this Report on Form 10-K, and to file the same, with exhibits thereto and other documents in connection therewith, with the Securities and Exchange Commission, hereby ratifying and confirming all that each of said attorneys-in-fact, or his substitute or substitutes, may do or cause to be done by virtue hereof.

    Pursuant to the requirements of the Securities Exchange Act of 1934, this Report has been signed below by the following persons on the 23rd day of March, 2001 on behalf of the Registrant and in the capacities indicated:

27

28

Report of Independent Accountants on
Financial Statement Schedule

To the Board of Directors of
Lattice Semiconductor Corporation:

    Our audits of the consolidated financial statements referred to in our report dated January 18, 2001 appearing in the 2000 Annual Report to Stockholders of Lattice Semiconductor Corporation (which report and consolidated financial statements are incorporated by reference in this Annual Report on Form 10-K) also included an audit of the financial statement schedule listed in Item 14(a)(2) of this Form 10-K. In our opinion, this financial statement schedule presents fairly, in all material respects, the information set forth therein when read in conjunction with the related consolidated financial statements.

Portland, Oregon
January 18, 2001

S-1

Schedule VIII

LATTICE SEMICONDUCTOR CORPORATION

VALUATION AND QUALIFYING ACCOUNTS

(In thousands)

(1)

Balance acquired in conjunction with our acquisition of Vantis Corporation on June 15, 1999.

S-2

QuickLinks